diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-30 16:28:48 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:08:32 +0000 |
| commit | 651f99f12b48729a2a786240679f9aeafcf1cf8b (patch) | |
| tree | f7e180121e10c6daf63ea8da7b985824118826bc /src/northbridge/intel/sandybridge/raminit_common.c | |
| parent | 6ad0ab1a693726c3fd5e9f68d1a8fc5b7535bd5e (diff) | |
nb/intel/sandybridge: use MESEG register names from datasheet
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.
Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit_common.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit_common.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b12ea25f25..0ba1678807 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -585,33 +585,33 @@ void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) pci_write_config32(PCI_DEV(0, 0, 0), BGSM, reg); if (me_uma_size) { - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK + 4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEMASK + 4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK + 4, reg); // ME base - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEBASE, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE, reg); - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEBASE + 4); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEBASE + 4, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEBASE + 4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_BASE + 4, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_BASE + 4, reg); // ME mask - reg = pci_read_config32(PCI_DEV(0, 0, 0), MEMASK); + reg = pci_read_config32(PCI_DEV(0, 0, 0), MESEG_MASK); val = (0x80000 - me_uma_size) & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); reg = reg | (1 << 10); // set lockbit on ME mem reg = reg | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MEMASK, reg); - pci_write_config32(PCI_DEV(0, 0, 0), MEMASK, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", MESEG_MASK, reg); + pci_write_config32(PCI_DEV(0, 0, 0), MESEG_MASK, reg); } } |