diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-12-13 16:37:53 +0100 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-25 21:41:28 +0000 |
commit | 5db1b15147ee1221cebd49455369713c0fd29b4a (patch) | |
tree | ec13e190d26c5c647be431ca0a496dbd6f356d60 /src/northbridge/intel/sandybridge/raminit.c | |
parent | 3170e9c0ef90dcbfb0b2e695fec3bd9d142d1db0 (diff) |
nb/intel/sandybridge: Rewrite constant values
Rewrite some constants to make their meaning somewhat clearer.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
-rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 8acfb98b57..1d4354c83d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -309,7 +309,7 @@ static void init_dram_ddr3(int s3resume, const u32 cpuid) wait_txt_clear(); - wrmsr(0x000002e6, (msr_t) { .lo = 0, .hi = 0 }); + wrmsr(0x2e6, (msr_t) { .lo = 0, .hi = 0 }); const u32 sskpd = MCHBAR32(SSKPD); // !!! = 0x00000000 if ((pci_read_config16(SOUTHBRIDGE, 0xa2) & 0xa0) == 0x20 && sskpd && !s3resume) { |