diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-23 23:18:03 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-26 10:19:21 +0000 |
| commit | efbed263dfc1f85b61f1e023682d4e885ed207aa (patch) | |
| tree | 1462c243c13402718bd63b6d2dd0cf4319e2bb3d /src/northbridge/intel/sandybridge/raminit.c | |
| parent | 29f391ec8f37e3e7d838bf2d16a4ba190062f1dc (diff) | |
nb/intel/sandybridge: Unify the code paths
The code for Sandy Bridge is a subset of the code for Ivy Bridge. Adapt
the Ivy Bridge code so that it also supports Sandy Bridge, and use it.
Tested on Asus P8Z77-V LX2, still boots with i7-2600 and i5-3330.
Change-Id: I7b78ec605aff976b9a5cdbb364a69df4b4947c6e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39737
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 93bfd4c540..b096a11bf2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -214,14 +214,6 @@ static void save_timings(ramctr_timing *ctrl) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } -static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) -{ - if (IS_SANDY_CPU(ctrl->cpu)) - return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size); - else - return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size); -} - static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; |