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authorAngel Pons <th3fanbus@gmail.com>2020-12-12 16:22:18 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-12-25 21:41:17 +0000
commit3170e9c0ef90dcbfb0b2e695fec3bd9d142d1db0 (patch)
treeb85200078ab5d0cff5159228a411cd1880d79b20 /src/northbridge/intel/sandybridge/raminit.c
parente0183d6540b8e8a8281f4317b881dfbc57f12bc4 (diff)
nb/intel/sandybridge: Allow to ignore XMP voltage
Native raminit only supports 1.5V operation, but there are DIMMs which request 1.65V operation in XMP profiles. Add an option to force XMP to be used when the requested voltage isn't supported, which will run the DIMMs at 1.5V with XMP timings. Consider this to be overclocking. Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
-rw-r--r--src/northbridge/intel/sandybridge/raminit.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 3077c0ae8f..8acfb98b57 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -200,7 +200,12 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
/* TODO: Support DDR3 voltages other than 1500mV */
printram("XMP profile's requested %u mV is unsupported.\n",
dimm->voltage);
- spd_decode_ddr3(dimm, spd[spd_slot]);
+
+ if (CONFIG(NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE))
+ printk(BIOS_WARNING,
+ "XMP requested voltage will be ignored.\n");
+ else
+ spd_decode_ddr3(dimm, spd[spd_slot]);
}
/* Fill in CRC16 for MRC cache */