diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2017-10-28 16:36:09 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-04-14 10:02:07 +0000 |
| commit | 05d4bf7ea76114dcbd21f8302e7152f40d806f18 (patch) | |
| tree | 77e6fa56dd6150a4010aa7f59f2de2183dc6c04e /src/northbridge/intel/sandybridge/raminit.c | |
| parent | 48d5b8d463ceccf5bf38f0d45490cb9d6185979e (diff) | |
nb/intel/sandybridge/raminit: Add ECC detection support
Add support for detection ECC capability and forced ECC mode.
Print the ECC mode in verbose debugging mode.
Change-Id: I5b7599746195cfa996a48320404a8dbe6820483a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/22214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/raminit.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/raminit.c | 30 |
1 files changed, 21 insertions, 9 deletions
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index b096a11bf2..a938a49172 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -214,6 +214,23 @@ static void save_timings(ramctr_timing *ctrl) mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, sizeof(*ctrl)); } +static void reinit_ctrl(ramctr_timing *ctrl, int min_tck, const u32 cpuid) +{ + /* Reset internal state */ + memset(ctrl, 0, sizeof(*ctrl)); + ctrl->tCK = min_tck; + + /* Get architecture */ + ctrl->cpu = cpuid; + + /* Get ECC support and mode */ + ctrl->ecc_forced = get_host_ecc_forced(); + ctrl->ecc_supported = ctrl->ecc_forced || get_host_ecc_cap(); + printk(BIOS_DEBUG, "ECC supported: %s ECC forced: %s\n", + ctrl->ecc_supported ? "yes" : "no", + ctrl->ecc_forced ? "yes" : "no"); +} + static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) { int me_uma_size, cbmem_was_inited, fast_boot, err; @@ -300,11 +317,10 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) } if (!fast_boot) { /* Reset internal state */ - memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck; + reinit_ctrl(&ctrl, min_tck, cpuid); - /* Get architecture */ - ctrl.cpu = cpuid; + printk(BIOS_INFO, "ECC RAM %s.\n", ctrl.ecc_forced ? "required" : + ctrl.ecc_supported ? "supported" : "unsupported"); /* Get DDR3 SPD data */ memset(spds, 0, sizeof(spds)); @@ -320,11 +336,7 @@ static void init_dram_ddr3(int min_tck, int s3resume, const u32 cpuid) printram("Disable failing channel.\n"); /* Reset internal state */ - memset(&ctrl, 0, sizeof(ctrl)); - ctrl.tCK = min_tck; - - /* Get architecture */ - ctrl.cpu = cpuid; + reinit_ctrl(&ctrl, min_tck, cpuid); /* Reset DDR3 frequency */ dram_find_spds_ddr3(spds, &ctrl); |