diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-03-16 23:17:32 +0100 |
---|---|---|
committer | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-18 21:42:05 +0000 |
commit | 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 (patch) | |
tree | a9d37cd90987d0c5e17c7a5bb1c6380c7cda8eef /src/northbridge/intel/sandybridge/pei_data.h | |
parent | 1cd7d3e664fcf119a2b2f5e3fd8824b5682c6807 (diff) |
nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/pei_data.h')
-rw-r--r-- | src/northbridge/intel/sandybridge/pei_data.h | 70 |
1 files changed, 38 insertions, 32 deletions
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 8e98becbe3..8114bcc153 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -33,10 +33,10 @@ #include <stdint.h> typedef struct { - uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto - uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable - uint16_t preboot_support; // 0: No xHCI preOS driver, 1: xHCI preOS driver - uint16_t xhci_streams; // 0: Disable, 1: Enable + uint16_t mode; /* 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto */ + uint16_t hs_port_switch_mask; /* 4 bit mask, 1: switchable, 0: not switchable */ + uint16_t preboot_support; /* 0: No xHCI preOS driver, 1: xHCI preOS driver */ + uint16_t xhci_streams; /* 0: Disable, 1: Enable */ } pch_usb3_controller_settings; typedef void (*tx_byte_func)(unsigned char byte); @@ -57,17 +57,19 @@ struct pei_data uint32_t pmbase; uint32_t gpiobase; uint32_t thermalbase; - uint32_t system_type; // 0 Mobile, 1 Desktop/Server + uint32_t system_type; /* 0 Mobile, 1 Desktop/Server */ uint32_t tseg_size; uint8_t spd_addresses[4]; uint8_t ts_addresses[4]; int boot_mode; int ec_present; int gbe_enable; - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel + /* + * 0 = leave channel enabled + * 1 = disable dimm 0 on channel + * 2 = disable dimm 1 on channel + * 3 = disable dimm 0+1 on channel + */ int dimm_channel0_disabled; int dimm_channel1_disabled; /* Seed values saved in CMOS */ @@ -90,46 +92,50 @@ struct pei_data * [1] = overcurrent pin * [2] = length * - * Ports 0-7 can be mapped to OC0-OC3 + * Ports 0-7 can be mapped to OC0-OC3 * Ports 8-13 can be mapped to OC4-OC7 * * Port Length * MOBILE: - * < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude) - * < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude) + * < 0x050 = Setting 1 (back panel, 1 to 5 in, lowest tx amplitude) + * < 0x140 = Setting 2 (back panel, 5 to 14 in, highest tx amplitude) * DESKTOP: - * < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude) - * < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude) - * < 0x150 = Setting 3 (back panel, 13-15in, highest tx amplitude) + * < 0x080 = Setting 1 (front/back panel, less than 8 in, lowest tx amplitude) + * < 0x130 = Setting 2 (back panel, 8 to 13 in, higher tx amplitude) + * < 0x150 = Setting 3 (back panel, 13 to 15 in, highest tx amplitude) */ uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. - * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" - * flag and the spd_addresses are used to determine which DIMMs should - * use the SPD from spd_data[0]. + /* + * SPD data array for onboard RAM. Note that spd_data [1..3] are ignored: instead, + * the "dimm_channel{0,1}_disabled" flag and the spd_addresses are used to determine + * which DIMMs should use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; int ddr3lv_support; - /* pcie_init needs to be set to 1 to have the system agent initialize - * PCIe. Note: This should only be required if your system has Gen3 devices - * and it will increase your boot time by at least 100ms. + /* + * pcie_init needs to be set to 1 to have the system agent initialize PCIe. + * Note: This should only be required if your system has Gen3 devices and + * it will increase your boot time by at least 100ms. */ int pcie_init; - /* N mode functionality. Leave this setting at 0. - * 0 Auto - * 1 1N - * 2 2N + /* + * N mode functionality. Leave this setting at 0. + * + * 0: Auto + * 1: 1N + * 2: 2N */ int nmode; - /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows - * for DIMM SPD data to specify whether double-rate is required for - * extended operating temperature range. - * 0 Enable double rate based upon temperature thresholds - * 1 Normal rate - * 2 Always enable double rate + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to + * specify whether double-rate is required for extended operating temperature range. + * + * 0: Enable double rate based upon temperature thresholds + * 1: Normal rate + * 2: Always enable double rate */ int ddr_refresh_rate_config; } __packed; |