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authorPatrick Rudolph <siro@das-labor.org>2017-07-05 20:07:06 +0200
committerMartin Roth <martinroth@google.com>2018-04-13 16:55:14 +0000
commit0b643d24994588480a3ca77ecacbb7ce66402195 (patch)
tree08754f880a954f7b9e9ce9c935cfc890c526d390 /src/northbridge/intel/sandybridge/pcie.c
parent70df5d6e43fd839d3fc7bf8fa672c4b540fc0c10 (diff)
nb/intel/sandybridge/peg: Add PEG driver stub
Required for other ACPI generators, like the one used for _ROM. * Add ACPI code for PEG10/PEG11/PEG12/PEG60 and include it on all platforms. * Add PCIe driver for PEG. The driver returns ACPI names for ssdt generators. Needs test on real hardware. Change-Id: I96835c43522580c95fd4f250c56bf9438e993bc1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22337 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/pcie.c')
-rw-r--r--src/northbridge/intel/sandybridge/pcie.c105
1 files changed, 105 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/pcie.c b/src/northbridge/intel/sandybridge/pcie.c
new file mode 100644
index 0000000000..9cb823e34c
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pcie.c
@@ -0,0 +1,105 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017-2018 Patrick Rudolph <siro@das-labor.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+
+static void pcie_disable(struct device *dev)
+{
+ printk(BIOS_INFO, "%s: Disabling device\n", dev_path(dev));
+ dev->enabled = 0;
+}
+
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+static const char *pcie_acpi_name(const struct device *dev)
+{
+ assert(dev);
+
+ if (dev->path.type != DEVICE_PATH_PCI)
+ return NULL;
+
+ assert(dev->bus);
+ if (dev->bus->secondary == 0)
+ switch (dev->path.pci.devfn) {
+ case PCI_DEVFN(1, 0):
+ return "PEGP";
+ case PCI_DEVFN(1, 1):
+ return "PEG1";
+ case PCI_DEVFN(1, 2):
+ return "PEG2";
+ case PCI_DEVFN(6, 0):
+ return "PEG6";
+ };
+
+ const device_t port = dev->bus->dev;
+ assert(port);
+ assert(port->bus);
+
+ if (dev->path.pci.devfn == PCI_DEVFN(0, 0) &&
+ port->bus->secondary == 0 &&
+ (port->path.pci.devfn == PCI_DEVFN(1, 0) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 1) ||
+ port->path.pci.devfn == PCI_DEVFN(1, 2) ||
+ port->path.pci.devfn == PCI_DEVFN(6, 0)))
+ return "DEV0";
+
+ return NULL;
+}
+#endif
+
+static void
+pcie_set_subsystem(struct device *dev, unsigned int ven, unsigned int device)
+{
+ /* NOTE: This is not the default position! */
+ if (!ven || !device)
+ pci_write_config32(dev, 0x94,
+ pci_read_config32(dev, 0));
+ else
+ pci_write_config32(dev, 0x94,
+ ((device & 0xffff) << 16) | (ven & 0xffff));
+}
+
+static struct pci_operations pci_ops = {
+ .set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .scan_bus = pciexp_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .disable = pcie_disable,
+ .init = pci_dev_init,
+ .ops_pci = &pci_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+ .acpi_name = pcie_acpi_name,
+#endif
+};
+
+static const unsigned short pci_device_ids[] = { 0x0101, 0x0105, 0x0109, 0x010d,
+ 0x0151, 0x0155, 0x0159, 0x015d,
+ 0 };
+
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};