diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 17:15:37 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-09-21 08:03:24 +0000 |
| commit | f950a7ec6767eee0a857d01e0c3f67ccf36dd8e1 (patch) | |
| tree | f6c6dea0f792c08e8423f290dc330d90197e433d /src/northbridge/intel/sandybridge/northbridge.c | |
| parent | dfca1697fc99613820cca791a95023afbf87c0eb (diff) | |
nb/intel/sandybridge: Clean up DMIBAR/EPBAR registers
Several registers have been copy-pasted from i945 and do not exist on
Sandy Bridge. Moreover, other register definitions were missing. Use the
newly-added definitions in existing code, in place of numerical offsets.
Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical.
Change-Id: I9ad849f57bc68256a2a87ffdc856c4b521e35892
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45357
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/northbridge.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e670c09cf0..541bf73bee 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -262,8 +262,8 @@ static void northbridge_dmi_init(struct device *dev) u32 reg32; /* Clear error status bits */ - DMIBAR32(0x1c4) = 0xffffffff; - DMIBAR32(0x1d0) = 0xffffffff; + DMIBAR32(DMIUESTS) = 0xffffffff; + DMIBAR32(DMICESTS) = 0xffffffff; /* Steps prior to DMI ASPM */ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { @@ -273,9 +273,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x250) = reg32; } - reg32 = DMIBAR32(0x238); + reg32 = DMIBAR32(DMILLTC); reg32 |= (1 << 29); - DMIBAR32(0x238) = reg32; + DMIBAR32(DMILLTC) = reg32; if (bridge_silicon_revision() >= SNB_STEP_D0) { reg32 = DMIBAR32(0x1f8); @@ -300,9 +300,9 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0xd04) = reg32; } - reg32 = DMIBAR32(0x88); + reg32 = DMIBAR32(DMILCTL); reg32 |= (1 << 1) | (1 << 0); - DMIBAR32(0x88) = reg32; + DMIBAR32(DMILCTL) = reg32; } /* Disable unused PEG devices based on devicetree */ |