nb/intel/sandybridge: Tidy up code and comments

- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)

With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.

Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 15 insertions, 13 deletions

diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c
index 03e8db6cd7..60b6dcdf31 100644
--- a/src/northbridge/intel/sandybridge/memmap.c
+++ b/src/northbridge/intel/sandybridge/memmap.c
@@ -26,18 +26,17 @@
 static uintptr_t smm_region_start(void)
 {
 	/* Base of TSEG is top of usable DRAM */
-	uintptr_t tom = pci_read_config32(PCI_DEV(0, 0, 0), TSEGMB);
-	return tom;
+	return pci_read_config32(HOST_BRIDGE, TSEGMB);
 }
 
 void *cbmem_top_chipset(void)
 {
-	return (void *) smm_region_start();
+	return (void *)smm_region_start();
 }
 
 static uintptr_t northbridge_get_tseg_base(void)
 {
-	return ALIGN_DOWN(smm_region_start(), 1*MiB);
+	return ALIGN_DOWN(smm_region_start(), 1 * MiB);
 }
 
 static size_t northbridge_get_tseg_size(void)
@@ -48,24 +47,27 @@ static size_t northbridge_get_tseg_size(void)
 void smm_region(uintptr_t *start, size_t *size)
 {
 	*start = northbridge_get_tseg_base();
-	*size = northbridge_get_tseg_size();
+	*size  = northbridge_get_tseg_size();
 }
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
+	uintptr_t top_of_ram = (uintptr_t)cbmem_top();
 
-	top_of_ram = (uintptr_t)cbmem_top();
-	/* Cache 8MiB below the top of ram. On sandybridge systems the top of
+	/*
+	 * Cache 8MiB below the top of ram. On sandybridge systems the top of
 	 * RAM under 4GiB is the start of the TSEG region. It is required to
 	 * be 8MiB aligned. Set this area as cacheable so it can be used later
-	 * for ramstage before setting up the entire RAM as cacheable. */
-	postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK);
+	 * for ramstage before setting up the entire RAM as cacheable.
+	 */
+	postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 8 * MiB, MTRR_TYPE_WRBACK);
 
-	/* Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
+	/*
+	 * Cache 8MiB at the top of ram. Top of RAM on sandybridge systems
 	 * is where the TSEG region resides. However, it is not restricted
 	 * to SMM mode until SMM has been relocated. By setting the region
 	 * to cacheable it provides faster access when relocating the SMM
-	 * handler as well as using the TSEG region for other purposes. */
-	postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK);
+	 * handler as well as using the TSEG region for other purposes.
+	 */
+	postcar_frame_add_mtrr(pcf, top_of_ram, 8 * MiB, MTRR_TYPE_WRBACK);
 }