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| author | Felix Held <felix-coreboot@felixheld.de> | 2019-12-30 16:28:48 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-01-01 16:08:32 +0000 |
| commit | 651f99f12b48729a2a786240679f9aeafcf1cf8b (patch) | |
| tree | f7e180121e10c6daf63ea8da7b985824118826bc /src/northbridge/intel/sandybridge/finalize.c | |
| parent | 6ad0ab1a693726c3fd5e9f68d1a8fc5b7535bd5e (diff) | |
nb/intel/sandybridge: use MESEG register names from datasheet
I used register names guessed on what the registers do, since the SNB
documentation marked those registers as reserved; the IVB documentation
(326765-005) has names for the registers, so I'll use those.
Change-Id: I2f1194438a56546d9836dd12635d064a900a2fd8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38008
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/finalize.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/finalize.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index fc970baee1..60e7a749ba 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -24,7 +24,7 @@ void intel_sandybridge_finalize_smm(void) pci_or_config16(PCI_DEV_SNB, GGC, 1 << 0); pci_or_config16(PCI_DEV_SNB, PAVPC, 1 << 2); pci_or_config32(PCI_DEV_SNB, DPR, 1 << 0); - pci_or_config32(PCI_DEV_SNB, MEMASK, 1 << 10); + pci_or_config32(PCI_DEV_SNB, MESEG_MASK, 1 << 10); pci_or_config32(PCI_DEV_SNB, REMAPBASE, 1 << 0); pci_or_config32(PCI_DEV_SNB, REMAPLIMIT, 1 << 0); pci_or_config32(PCI_DEV_SNB, TOM, 1 << 0); |