diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2012-06-23 20:14:07 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 23:50:59 +0200 |
| commit | fe7b5d2fa6705a2b553244dda0452ca55c5730a2 (patch) | |
| tree | 51a6edff273d0f348dbf8db8c48731550da0e726 /src/northbridge/intel/sandybridge/early_init.c | |
| parent | 22935e1f43c2b0873dfa9b5f176df5616ce7a041 (diff) | |
Ivybridge: fix workaround and enable PAIR
MCHBAR 0x5f10[7:0] should be set to 0x30 for ivybridge
and 0x20 for sandybridge. Move this code to ramstage
and set it per-chipset.
Power Aware Interrupt Routing is supported in ivybridge,
enable it and set fixed priority.
Boot on ivybridge device and read MCHBAR 0x5f10:
mmio_read8 0xfed15f10
0x30
And verify PAIR is enabled (bit4=1):
mmio_read8 0xfed15418
0x24
Change-Id: If017d5ce2bd5ab5092c86f657434f2b645ee6613
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1303
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/early_init.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 48faf5fb73..c7afa115cb 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -108,8 +108,6 @@ static void sandybridge_setup_graphics(void) pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8); /* Erratum workarounds */ - MCHBAR8(0x5f10) = 0x20; - reg32 = MCHBAR32(0x5f00); reg32 |= (1 << 9)|(1 << 10); MCHBAR32(0x5f00) = reg32; |