diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 01:22:20 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:29:14 +0000 |
| commit | d9e58dca9e72ca2efa62eab832aad606c9c58fcd (patch) | |
| tree | 565e2a763d0e70c2efcc0ce744599829679a275c /src/northbridge/intel/sandybridge/early_init.c | |
| parent | a2a9e607b1e92f322da25d0ca23ce565eb2b17d7 (diff) | |
nb/intel/sandybridge: Use common {DMI,EP,MCH}BAR accessors
Drop unused sandybridge.h includes to avoid build failures on Ironlake.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: If2f0147fe50266e2fe2098cafdf004e51282f5e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/sandybridge/early_init.c')
| -rw-r--r-- | src/northbridge/intel/sandybridge/early_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 45b5b8f10a..42957e540b 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -50,12 +50,12 @@ static void sandybridge_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, EPBAR + 4, (0LL + DEFAULT_EPBAR) >> 32); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR + 4, (0LL + DEFAULT_MCHBAR) >> 32); - pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR + 4, (0LL + DEFAULT_DMIBAR) >> 32); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, EPBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR + 4, 0); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR + 4, 0); printk(BIOS_DEBUG, " done\n"); } |