diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-16 23:17:32 +0100 |
|---|---|---|
| committer | Matt DeVillier <matt.devillier@gmail.com> | 2020-03-18 21:42:05 +0000 |
| commit | 7c49cb8f9ca86e791c392da40e7f0d3cb7ed47f3 (patch) | |
| tree | a9d37cd90987d0c5e17c7a5bb1c6380c7cda8eef /src/northbridge/intel/sandybridge/chip.h | |
| parent | 1cd7d3e664fcf119a2b2f5e3fd8824b5682c6807 (diff) | |
nb/intel/sandybridge: Tidy up code and comments
- Reformat some lines of code
- Move MCHBAR registers and documentation into a separate file
- Add a few missing macros
- Rename some registers
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
With BUILD_TIMELESS=1, this commit does not change the result of:
- Asus P8Z77-V LX2 with native raminit.
- Asus P8Z77-M PRO with MRC raminit.
Change-Id: I6e113e48afd685ca63cfcb11ff9fcf9df6e41e46
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39599
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/chip.h')
| -rw-r--r-- | src/northbridge/intel/sandybridge/chip.h | 24 |
1 files changed, 13 insertions, 11 deletions
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index 5f5bf31f34..83181567a5 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -19,9 +19,9 @@ /* * Digital Port Hotplug Enable: - * 0x04 = Enabled, 2ms short pulse + * 0x04 = Enabled, 2ms short pulse * 0x05 = Enabled, 4.5ms short pulse - * 0x06 = Enabled, 6ms short pulse + * 0x06 = Enabled, 6ms short pulse * 0x07 = Enabled, 100ms short pulse */ struct northbridge_intel_sandybridge_config { @@ -48,7 +48,7 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; /* - * Maximum PCI mmio size in MiB. + * Maximum PCI MMIO size in MiB. */ u16 pci_mmio_size; @@ -63,7 +63,8 @@ struct northbridge_intel_sandybridge_config { bool ec_present; bool ddr3lv_support; - /* N mode functionality. Leave this setting at 0. + /* + * N mode functionality. Leave this setting at 0. * 0 Auto * 1 1N * 2 2N @@ -74,12 +75,13 @@ struct northbridge_intel_sandybridge_config { DDR_NMODE_2N, } nmode; - /* DDR refresh rate config. JEDEC Standard No.21-C Annex K allows - * for DIMM SPD data to specify whether double-rate is required for - * extended operating temperature range. - * 0 Enable double rate based upon temperature thresholds - * 1 Normal rate - * 2 Always enable double rate + /* + * DDR refresh rate config. JEDEC Standard No.21-C Annex K allows for DIMM SPD data to + * specify whether double-rate is required for extended operating temperature range. + * + * 0 Enable double rate based upon temperature thresholds + * 1 Normal rate + * 2 Always enable double rate */ enum { DDR_REFRESH_RATE_TEMP_THRES = 0, @@ -93,7 +95,7 @@ struct northbridge_intel_sandybridge_config { * [1] = overcurrent pin * [2] = length * - * Ports 0-7 can be mapped to OC0-OC3 + * Ports 0-7 can be mapped to OC0-OC3 * Ports 8-13 can be mapped to OC4-OC7 * * Port Length |