diff options
| author | Alexander Couzens <lynxis@fe80.eu> | 2016-03-09 14:36:46 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-11 19:00:14 +0100 |
| commit | 92fc072c2faf3d1be82f50ee3feda42461e9ac16 (patch) | |
| tree | df2232c7db3a895bbf854fe87a73ac2f2dac13e6 /src/northbridge/intel/sandybridge/Makefile.inc | |
| parent | 81c5c761b305dd62019759e5e39248b02c0af820 (diff) | |
northbridge/intel: move mrccache.c of sandybridge + haswell to common
The sourcecode is 99% the same. Only two lines differ, but not
in functionality.
Also rename mrccache.c -> mrc_cache.c
Tested-on: boot + suspend/resume on x220
Change-Id: I36f79d066336f223b608c70c847ea6ea6e4ad287
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/14007
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/Makefile.inc')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Makefile.inc | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 4a7a854bee..b1bc2ac223 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -22,7 +22,6 @@ ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_sandybridge_lvds.c ramstage-$(CONFIG_SANDYBRIDGE_IVYBRIDGE_LVDS) += gma_ivybridge_lvds.c ramstage-y += acpi.c -ramstage-y += mrccache.c romstage-y += ram_calc.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -36,7 +35,6 @@ mrc.bin-position := 0xfffa0000 mrc.bin-type := mrc endif romstage-y += romstage.c -romstage-y += mrccache.c romstage-y += iommu.c romstage-y += early_init.c romstage-y += report_platform.c |