diff options
| author | Stefan Reinauer <reinauer@chromium.org> | 2012-06-06 13:24:32 -0700 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2012-07-24 06:55:35 +0200 |
| commit | 48214899c3e74d590ad45f1b8e98f745f2c6b2d0 (patch) | |
| tree | 6a0272e8be9a863349fef3ff25713a033fd73638 /src/northbridge/intel/sandybridge/Kconfig | |
| parent | 305b19dd7a8394132216f51acf2bc073c7c42397 (diff) | |
Fix MRC cache update delays
When no valid MRC cache area is found, the mrc_cache data structure
was used without prior initialization. This sometimes caused a long
delay when booting because compute_ip_checksum would checksum up to
4GB of memory.
Change-Id: I6a0ca1aa618838bbc3d042be425700fc34b427f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1277
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/sandybridge/Kconfig')
| -rw-r--r-- | src/northbridge/intel/sandybridge/Kconfig | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 67b3defb75..7dfd10d3ba 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -78,6 +78,24 @@ config CACHE_MRC_SIZE_KB int default 512 +# FIXME: build from rom size +config MRC_CACHE_BASE + hex + default 0xff800000 + +config MRC_CACHE_LOCATION + hex + default 0x370000 + +config MRC_CACHE_SIZE + hex + default 0x10000 + +config MRC_CACHE_ALIGNMENT + hex + default 0x1000 + + config DCACHE_RAM_BASE hex default 0xff7e0000 |