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authorAngel Pons <th3fanbus@gmail.com>2021-01-20 14:58:32 +0100
committerAngel Pons <th3fanbus@gmail.com>2021-01-30 23:11:36 +0000
commit10f9b83f534bdc89e00f0a02befd952ae8d7f829 (patch)
tree01b2bf7eaa935ec979921a956528c9fafb9faa28 /src/northbridge/intel/sandybridge/Kconfig
parent32770f840d768b46d123893ecb87bb9095e4655d (diff)
nb/intel/sandybridge: Define and use MMCONF_BUS_NUMBER
Change-Id: Id88c18129bb773d979ad84bd0bb47188d74d4bc4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49762 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/sandybridge/Kconfig')
-rw-r--r--src/northbridge/intel/sandybridge/Kconfig4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 0ec4ba2971..16cd697374 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -90,6 +90,10 @@ config MMCONF_BASE_ADDRESS
help
The MRC blob requires it to be at 0xf0000000.
+config MMCONF_BUS_NUMBER
+ int
+ default 64
+
config DCACHE_RAM_BASE
hex
default 0xfefe0000