diff options
author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-05-22 02:18:00 +0300 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2019-01-06 01:17:54 +0000 |
commit | c70eed1e6202c928803f3e7f79161cd247a62b23 (patch) | |
tree | e46a6c87f6f13b7719fd40a9360d8d03359bfffb /src/northbridge/intel/pineview | |
parent | 54efaae701dacd58621e66a8cf56812eb5304946 (diff) |
device: Use pcidev_on_root()
Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/26484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/pineview')
-rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 2 | ||||
-rw-r--r-- | src/northbridge/intel/pineview/gma.c | 4 | ||||
-rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 7f90529ef2..89744289a2 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -41,7 +41,7 @@ static void early_graphics_setup(void) u16 reg16; u32 reg32; - const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0)); + const struct device *d0f0 = pcidev_on_root(0, 0); const struct northbridge_intel_pineview_config *config = d0f0->chip_info; pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e075ac136c..56242ceafe 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -72,7 +72,7 @@ void gma_set_gnvs_aslb(void *gnvs, uintptr_t aslb) static int gtt_setup(u8 *mmiobase) { u32 gttbase; - struct device *dev = dev_find_slot(0, PCI_DEVFN(0,0)); + struct device *dev = pcidev_on_root(0, 0); gttbase = pci_read_config32(dev, BGSM); printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase); @@ -319,7 +319,7 @@ static void gma_set_subsystem(struct device *dev, unsigned int vendor, const struct i915_gpu_controller_info *intel_gma_get_controller_info(void) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + struct device *dev = pcidev_on_root(0x2, 0); if (!dev) { printk(BIOS_WARNING, "WARNING: Can't find IGD (0,2,0)\n"); return NULL; diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 33e8089f49..ee1efd3b1e 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -60,7 +60,7 @@ static void mch_domain_read_resources(struct device *dev) u16 index; const u32 top32memk = 4 * (GiB / KiB); - struct device *mch = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *mch = pcidev_on_root(0, 0); index = 3; @@ -143,7 +143,7 @@ static void mch_domain_read_resources(struct device *dev) void northbridge_write_smram(u8 smram) { - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_on_root(0, 0); if (dev == NULL) die("could not find pci 00:00.0!\n"); |