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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-15 20:14:33 +0100 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-25 15:49:27 +0000 |
| commit | 99e578e3c1697028957f25efc7c14d1cb4d405dc (patch) | |
| tree | 44853df46744994d5caf3172a579f9d92252155b /src/northbridge/intel/pineview/romstage.c | |
| parent | c752c500fbcc055e8cdfb30a2e523e8a9349b79f (diff) | |
nb/intel/pineview: Move to C_ENVIRONMENT_BOOTBLOCK
This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/pineview/romstage.c')
| -rw-r--r-- | src/northbridge/intel/pineview/romstage.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index 41fb0f6720..8d7de45149 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -57,20 +57,12 @@ void mainboard_romstage_entry(unsigned long bist) if (bist == 0) enable_lapic(); - /* Disable watchdog timer */ - RCBA32(GCS) = RCBA32(GCS) | 0x20; - /* Enable GPIOs */ pci_write_config32(LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&mainboard_gpio_map); - mb_enable_lpc(); // nm10_enable_lpc - - /* Initialize console device(s) */ - console_init(); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); |