diff options
author | Angel Pons <th3fanbus@gmail.com> | 2021-02-06 15:03:48 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-07 21:59:51 +0000 |
commit | 94eea6fe16e2b868f892aafd7c5ed5042dc35c7f (patch) | |
tree | 75fdf87d57796f6ed2a1f8a736edaaa26ae3ecd3 /src/northbridge/intel/pineview/raminit.c | |
parent | 896a1f7609d87fdb1eb18e1673622533d9abf04d (diff) |
nb/intel/pineview: Rewrite hex values in lowercase
Most hex values are already lowercase. For consistency reasons, rewrite
uppercase hex values in lowercase.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I185b448ca7822fa89c57efe788e05b582b259c37
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50356
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview/raminit.c')
-rw-r--r-- | src/northbridge/intel/pineview/raminit.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index f39f9e328d..965adaef2f 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -535,12 +535,12 @@ static void sdram_clk_crossing(struct sysinfo *s) u8 ddr_freq, fsb_freq; static const u32 clkcross[2][2][4] = { { - {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, /* FSB = 667, DDR = 667 */ - {0x1F1F1F1F, 0x2A1F1FA5, 0x00000000, 0x05000002}, /* FSB = 667, DDR = 800 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000}, /* FSB = 667, DDR = 667 */ + {0x1f1f1f1f, 0x2a1f1fa5, 0x00000000, 0x05000002}, /* FSB = 667, DDR = 800 */ }, { - {0x1F1F1F1F, 0x0D07070B, 0x00000000, 0x00000000}, /* FSB = 800, DDR = 667 */ - {0xFFFFFFFF, 0x05030305, 0x0000FFFF, 0x00000000}, /* FSB = 800, DDR = 800 */ + {0x1f1f1f1f, 0x0d07070b, 0x00000000, 0x00000000}, /* FSB = 800, DDR = 667 */ + {0xffffffff, 0x05030305, 0x0000ffff, 0x00000000}, /* FSB = 800, DDR = 800 */ }, }; @@ -620,8 +620,8 @@ static void sdram_clkmode(struct sysinfo *s) MCHBAR32_OR(C0STATRDCTRL, 1 << 23); const u32 cas_to_reg[2][4] = { - {0x00000000, 0x00030100, 0x0C240201, 0x00000000}, /* DDR = 667 */ - {0x00000000, 0x00030100, 0x0C240201, 0x10450302} /* DDR = 800 */ + {0x00000000, 0x00030100, 0x0c240201, 0x00000000}, /* DDR = 667 */ + {0x00000000, 0x00030100, 0x0c240201, 0x10450302} /* DDR = 800 */ }; MCHBAR32(C0GNT2LNCH2) = cas_to_reg[ddr_freq][s->selected_timings.CAS - 3]; @@ -1204,14 +1204,14 @@ static void sdram_dlltiming(struct sysinfo *s) #define C0RCOMPCTRLx(x) (rcompctl[(x)] + 0x00) #define C0RCOMPMULTx(x) (rcompctl[(x)] + 0x04) #define C0RCOMPOVRx(x) (rcompctl[(x)] + 0x06) -#define C0RCOMPOSVx(x) (rcompctl[(x)] + 0x0A) -#define C0SCOMPVREFx(x) (rcompctl[(x)] + 0x0E) +#define C0RCOMPOSVx(x) (rcompctl[(x)] + 0x0a) +#define C0SCOMPVREFx(x) (rcompctl[(x)] + 0x0e) #define C0SCOMPOVRx(x) (rcompctl[(x)] + 0x10) #define C0SCOMPOFFx(x) (rcompctl[(x)] + 0x12) #define C0DCOMPx(x) (rcompctl[(x)] + 0x14) #define C0SLEWBASEx(x) (rcompctl[(x)] + 0x16) #define C0SLEWPULUTx(x) (rcompctl[(x)] + 0x18) -#define C0SLEWPDLUTx(x) (rcompctl[(x)] + 0x1C) +#define C0SLEWPDLUTx(x) (rcompctl[(x)] + 0x1c) #define C0DCOMPOVRx(x) (rcompctl[(x)] + 0x20) #define C0DCOMPOFFx(x) (rcompctl[(x)] + 0x24) @@ -1319,7 +1319,7 @@ static void sdram_rcomp(struct sysinfo *s) rcomp1 = 0x00050542; } if (s->selected_timings.fsb_clock == FSB_CLOCK_667MHz) { - rcomp2 = 0x14C42827; + rcomp2 = 0x14c42827; } else { rcomp2 = 0x19042827; } |