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| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:31:09 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:32 +0000 |
| commit | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (patch) | |
| tree | 7c55e861f5f04f058402f449975d7b4938d3e755 /src/northbridge/intel/pineview/pineview.h | |
| parent | b274ec73ab608384c925876d5a3bcf0396dcc3d5 (diff) | |
nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview/pineview.h')
| -rw-r--r-- | src/northbridge/intel/pineview/pineview.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h index cafda8ace6..64948c0e38 100644 --- a/src/northbridge/intel/pineview/pineview.h +++ b/src/northbridge/intel/pineview/pineview.h @@ -68,7 +68,6 @@ void pineview_early_init(void); u32 decode_igd_memory_size(const u32 gms); u32 decode_igd_gtt_size(const u32 gsm); -int decode_pcie_bar(u32 *const base, u32 *const len); /* Mainboard romstage callback functions */ void get_mb_spd_addrmap(u8 *spd_addr_map); |