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| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 15:40:54 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:27:16 +0000 |
| commit | 653d8717ba8d785af4e4eafca2416e1da2988f5d (patch) | |
| tree | 366317d6807b347467e964a2979d35859b71a959 /src/northbridge/intel/pineview/northbridge.c | |
| parent | 69356489fe43ca36f5ed20b7b92dc2cd0641803d (diff) | |
nb/intel/pineview: Change signature of `decode_pciebar`
Rename it and make it return an int, like other northbridges do.
Change-Id: Id526ff893320a77e96767ec642c196c2196f84e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/pineview/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/pineview/northbridge.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index e005bc9dfc..a04b62b5d5 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -114,7 +114,7 @@ static void mch_domain_read_resources(struct device *dev) (touud - top32memk) >> 10); } - if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x size=0x%x\n", pcie_config_base, pcie_config_size); |