nb/intel/pineview: Use `MiB` definition

Also constify a local variable while we're at it.

Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.

Change-Id: I90ab35932d7c0ba99ca16732b9616f3a15d972dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

1 files changed, 5 insertions, 4 deletions

diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c
index ad89aef04d..bcf1487001 100644
--- a/src/northbridge/intel/pineview/memmap.c
+++ b/src/northbridge/intel/pineview/memmap.c
@@ -3,6 +3,7 @@
 #define __SIMPLE_DEVICE__
 
 #include <arch/romstage.h>
+#include <commonlib/helpers.h>
 #include <device/pci_ops.h>
 #include <device/device.h>
 #include <device/pci_def.h>
@@ -51,7 +52,7 @@ u8 decode_pciebar(u32 *const base, u32 *const len)
 	}
 
 	*base = pciexbar;
-	*len = max_buses << 20;
+	*len = max_buses * MiB;
 	return 1;
 }
 
@@ -87,11 +88,11 @@ static u32 decode_tseg_size(const u32 esmramc)
 
 	switch ((esmramc >> 1) & 3) {
 	case 0:
-		return 1 << 20;
+		return 1 * MiB;
 	case 1:
-		return 2 << 20;
+		return 2 * MiB;
 	case 2:
-		return 8 << 20;
+		return 8 * MiB;
 	case 3:
 	default:
 		die("Bad TSEG setting.\n");