diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 12:00:31 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:29:46 +0000 |
| commit | 24b1d8af060fa0aabb8b127716ba5c5ed87f5edf (patch) | |
| tree | 9e2c324a1ebb51d0d448f4199a410642fa0ca0b6 /src/northbridge/intel/pineview/early_init.c | |
| parent | a8df6cff16d4f24a7f6dfedd5979d0948ddda189 (diff) | |
nb/intel/pineview: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: Ic390d3431e2aa9f5f59cb266d4c358d0eb48576c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/pineview/early_init.c')
| -rw-r--r-- | src/northbridge/intel/pineview/early_init.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index 42a68d8c02..ce2398496c 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -136,9 +136,9 @@ static void pineview_setup_bars(void) pci_write_config8(HOST_BRIDGE, 0x08, 0x69); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(HOST_BRIDGE, EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(HOST_BRIDGE, MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(HOST_BRIDGE, DMIBAR, DEFAULT_DMIBAR | 1); + pci_write_config32(HOST_BRIDGE, EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(HOST_BRIDGE, DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); pci_write_config32(HOST_BRIDGE, PMIOBAR, DEFAULT_PMIOBAR | 1); /* Set C0000-FFFFF to access RAM on both reads and writes */ |