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| author | Angel Pons <th3fanbus@gmail.com> | 2020-03-09 21:39:44 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:09:19 +0000 |
| commit | 39ff703aa989ebdc056dd27e181fd135a551f522 (patch) | |
| tree | 61c38b71557a22d5b553f17849c12ffc802cec8e /src/northbridge/intel/pineview/bootblock.c | |
| parent | 099975debd89e72a1f2ea3a62dc1b9685b95533f (diff) | |
nb/intel/pineview: Clean up code and comments
- Reformat some lines of code
- Put names to all MCHBAR registers in a separate file
- Rewrite several comments
- Use C-style comments for consistency
- Rewrite some hex constants
- Use HOST_BRIDGE instead of PCI_DEV(0, 0, 0)
- Align a bunch of things
Tested with BUILD_TIMELESS=1, foxconn/d41s remains unaffected.
Change-Id: I29104b0c24d66c6f49844f99d62ec433bb31bdaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/northbridge/intel/pineview/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/pineview/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/bootblock.c b/src/northbridge/intel/pineview/bootblock.c index 98085a7406..83917c2332 100644 --- a/src/northbridge/intel/pineview/bootblock.c +++ b/src/northbridge/intel/pineview/bootblock.c @@ -20,6 +20,6 @@ void bootblock_early_northbridge_init(void) { - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, + pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | MMCONF_256_BUSSES | ENABLE); } |