diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:31:09 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:32 +0000 |
| commit | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (patch) | |
| tree | 7c55e861f5f04f058402f449975d7b4938d3e755 /src/northbridge/intel/pineview/acpi/pineview.asl | |
| parent | b274ec73ab608384c925876d5a3bcf0396dcc3d5 (diff) | |
nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview/acpi/pineview.asl')
| -rw-r--r-- | src/northbridge/intel/pineview/acpi/pineview.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/pineview/acpi/pineview.asl b/src/northbridge/intel/pineview/acpi/pineview.asl index 5fb2b1233e..4620c4f541 100644 --- a/src/northbridge/intel/pineview/acpi/pineview.asl +++ b/src/northbridge/intel/pineview/acpi/pineview.asl @@ -17,7 +17,7 @@ Device (PDRC) Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) - Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, 0x10000000) + Memory32Fixed(ReadWrite, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_MMCONF_LENGTH) Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) /* Misc ICH */ Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) /* Misc ICH */ |