diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:31:09 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:12:32 +0000 |
| commit | 1318ab475ddcae5fdd8f41b66c4d7034c8b3d396 (patch) | |
| tree | 7c55e861f5f04f058402f449975d7b4938d3e755 /src/northbridge/intel/pineview/acpi.c | |
| parent | b274ec73ab608384c925876d5a3bcf0396dcc3d5 (diff) | |
nb/intel/pineview: Define and use MMCONF_BUS_NUMBER
Note that bootblock.c originally wrote a reserved bit of the PCIEXBAR
register. The `length` bitfield was set to 0, so assume 256 busses.
Change-Id: Ie967747b4bf559b5aedc67cbcd35bca51f5a692e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49760
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/pineview/acpi.c')
| -rw-r--r-- | src/northbridge/intel/pineview/acpi.c | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/src/northbridge/intel/pineview/acpi.c b/src/northbridge/intel/pineview/acpi.c index 9d85717d63..a04cb0b45a 100644 --- a/src/northbridge/intel/pineview/acpi.c +++ b/src/northbridge/intel/pineview/acpi.c @@ -2,21 +2,12 @@ #include <acpi/acpigen.h> #include <acpi/acpi.h> -#include <commonlib/helpers.h> #include <device/device.h> -#include <northbridge/intel/pineview/pineview.h> -#include <types.h> unsigned long acpi_fill_mcfg(unsigned long current) { - u32 length, pciexbar; - - if (!decode_pcie_bar(&pciexbar, &length)) - return current; - - const int max_buses = length / MiB; - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, pciexbar, 0, 0, - max_buses - 1); + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, CONFIG_MMCONF_BUS_NUMBER - 1); return current; } |