intel/gma: consolidate vbt code

Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6800
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>

4 files changed, 18 insertions, 144 deletions

diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c
index 9b7357c64a..6f694e268d 100644
--- a/src/northbridge/intel/nehalem/acpi.c
+++ b/src/northbridge/intel/nehalem/acpi.c
@@ -31,6 +31,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <drivers/intel/gma/intel_bios.h>
 #include <build.h>
 #include <arch/acpigen.h>
 #include <cpu/cpu.h>
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h
index e33d1082d1..1a31238402 100644
--- a/src/northbridge/intel/nehalem/chip.h
+++ b/src/northbridge/intel/nehalem/chip.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <drivers/intel/gma/i915.h>
+
 /*
  * Digital Port Hotplug Enable:
  *  0x04 = Enabled, 2ms short pulse
@@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config {
 	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
 	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
 
-	int gpu_use_spread_spectrum_clock;
-	int gpu_lvds_dual_channel;
-	int gpu_link_frequency_270_mhz;
-	int gpu_lvds_num_lanes;
+	struct i915_gpu_controller_info gfx;
 };
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index a57bf6bd88..c3e2a492cf 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 	u32 pixel_n = 1;
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000;
+	u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
 	u32 data_m1;
 	u32 data_n1 = 0x00800000;
 	u32 link_m1;
@@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 	hfront_porch = edid.hso;
 	vfront_porch = edid.vso;
 
-	target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock
+	target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
 		: (2 * edid.pixel_clock);
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
 	vga_textmode_init();
@@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 
 	link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
 	data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
-		/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4));
+		/ (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
 
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
@@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 	       hsync, vsync);
 	printk(BIOS_DEBUG, "Front porch %d x %d\n",
 	       hfront_porch, vfront_porch);
-	printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock
+	printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG,
-	       info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
+	       info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
 	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
 	write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
-	write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock
+	write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock
 					  ? 0x1002 : 0x400));
 	mdelay(1);
 	write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 		| ((pixel_m1 - 2) << 8) | pixel_m2);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	mdelay(1);
 	write32(mmio + _PCH_DPLL(0),
 		DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
-		| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
+		| (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
 		   : DPLLB_LVDS_P2_CLOCK_DIV_14)
 		| (0x10000 << (pixel_p1 - 1))
-		| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13)
+		| ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
 		| (0x1 << (pixel_p1 - 1)));
 	/* Re-lock the registers.  */
 	write32(mmio + PCH_PP_CONTROL,
@@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 
 	write32(mmio + PCH_LVDS,
 		(hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 	write32(mmio + PCH_LVDS,
 		LVDS_PORT_ENABLE
 		| (hpolarity << 20) | (vpolarity << 21)
-		| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
+		| (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
 		   | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
 		| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
 		| LVDS_DETECTED);
@@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
 #endif
 }
 
-static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf,
-			   void *vbt)
-{
-	struct vbt_header *head = vbt;
-	struct bdb_header *bdb_head;
-	struct bdb_general_features *genfeat;
-	u8 *ptr;
-
-	memset(head, 0, sizeof (*head));
-
-	memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20);
-	head->version = 100;
-	head->header_size = sizeof (*head);
-	head->bdb_offset = sizeof (*head);
-
-	bdb_head = (struct bdb_header *) (head + 1);
-	memset(bdb_head, 0, sizeof (*bdb_head));
-	memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
-	bdb_head->version = 0xa8;
-	bdb_head->header_size = sizeof (*bdb_head);
-
-	ptr = (u8 *) (bdb_head + 1);
-
-	ptr[0] = BDB_GENERAL_FEATURES;
-	ptr[1] = sizeof (*genfeat);
-	ptr[2] = sizeof (*genfeat) >> 8;
-	ptr += 3;
-
-	genfeat = (struct bdb_general_features *) ptr;
-	memset(genfeat, 0, sizeof (*genfeat));
-	genfeat->panel_fitting = 3;
-	genfeat->flexaim = 1;
-	genfeat->download_ext_vbt = 1;
-	genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
-	genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
-	genfeat->rsvd10 = 0x4;
-	genfeat->legacy_monitor_detect = 1;
-	genfeat->int_crt_support = 1;
-	genfeat->dp_ssc_enb = 1;
-
-	ptr += sizeof (*genfeat);
-
-	bdb_head->bdb_size = ptr - (u8 *)bdb_head;
-	head->vbt_size = ptr - (u8 *)head;
-	head->vbt_checksum = 0;
-	return ptr - (u8 *)head;
-}
 #endif
 
 static void gma_func0_init(struct device *dev)
@@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev)
 	}
 
 	/* Linux relies on VBT for panel info.  */
-	if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) {
-		optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
-		optionrom_pcir_t *pcir;
-		size_t vbt_size;
-		size_t fake_oprom_size;
-
-		memset(oh, 0, 8192);
-
-		oh->signature = OPROM_SIGNATURE;
-		oh->pcir_offset = 0x40;
-		oh->vbt_offset = 0x80;
-
-		pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
-		pcir->signature = 0x52494350;	// PCIR
-		pcir->vendor = dev->vendor;
-		pcir->device = dev->device;
-		pcir->length = sizeof(*pcir);
-		pcir->revision = dev->class;
-		pcir->classcode[0] = dev->class >> 8;
-		pcir->classcode[1] = dev->class >> 16;
-		pcir->classcode[2] = dev->class >> 24;
-		pcir->indicator = 0x80;
-
-		vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
-		fake_oprom_size = (0x80 + vbt_size + 511) / 512;
-		oh->size = fake_oprom_size;
-		pcir->imagelength = fake_oprom_size;
-	}
+	generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
 #endif
 
 
diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h
index fdea85a436..f0e1c537f3 100644
--- a/src/northbridge/intel/nehalem/gma.h
+++ b/src/northbridge/intel/nehalem/gma.h
@@ -118,56 +118,4 @@ typedef struct {
 	opregion_vbt_t vbt;
 } __attribute__((packed)) igd_opregion_t;
 
-/* Intel Video BIOS (Option ROM) */
-typedef struct {
-	u16	signature;
-	u8	size;
-	u8	reserved[21];
-	u16	pcir_offset;
-	u16	vbt_offset;
-} __attribute__((packed)) optionrom_header_t;
-
-#define OPROM_SIGNATURE 0xaa55
-
-typedef struct {
-	u32 signature;
-	u16 vendor;
-	u16 device;
-	u16 reserved1;
-	u16 length;
-	u8  revision;
-	u8  classcode[3];
-	u16 imagelength;
-	u16 coderevision;
-	u8  codetype;
-	u8  indicator;
-	u16 reserved2;
-} __attribute__((packed)) optionrom_pcir_t;
-
-typedef struct {
-	u8  hdr_signature[20];
-	u16 hdr_version;
-	u16 hdr_size;
-	u16 hdr_vbt_size;
-	u8  hdr_vbt_checksum;
-	u8  hdr_reserved;
-	u32 hdr_vbt_datablock;
-	u32 hdr_aim[4];
-	u8  datahdr_signature[16];
-	u16 datahdr_version;
-	u16 datahdr_size;
-	u16 datahdr_datablocksize;
-	u8  coreblock_id;
-	u16 coreblock_size;
-	u16 coreblock_biossize;
-	u8  coreblock_biostype;
-	u8  coreblock_releasestatus;
-	u8  coreblock_hwsupported;
-	u8  coreblock_integratedhw;
-	u8  coreblock_biosbuild[4];
-	u8  coreblock_biossignon[155];
-} __attribute__((packed)) optionrom_vbt_t;
-
-#define VBT_SIGNATURE 0x54425624
-
 #endif