cpu/intel/model_2065x: Put stage cache in TSEG

TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.

Change-Id: I89cbfb6ece62f554ac676fe686115e841d2c1e40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>

2 files changed, 6 insertions, 7 deletions

diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c
index 233b0bbd00..485cb27f45 100644
--- a/src/northbridge/intel/nehalem/northbridge.c
+++ b/src/northbridge/intel/nehalem/northbridge.c
@@ -171,13 +171,6 @@ static void mc_read_resources(struct device *dev)
 	add_fixed_resources(dev, 10);
 }
 
-u32 northbridge_get_tseg_base(void)
-{
-	struct device *dev = pcidev_on_root(0, 0);
-
-	return pci_read_config32(dev, TSEG) & ~1;
-}
-
 u32 northbridge_get_tseg_size(void)
 {
 	return CONFIG_SMM_TSEG_SIZE;
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 163f21ce3c..ca821da2dc 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -23,6 +23,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <program_loading.h>
+#include <cpu/intel/smm/gen1/smi.h>
 #include "nehalem.h"
 
 static uintptr_t smm_region_start(void)
@@ -32,6 +33,11 @@ static uintptr_t smm_region_start(void)
 	return tom;
 }
 
+u32 northbridge_get_tseg_base(void)
+{
+	return (u32)smm_region_start & ~1;
+}
+
 void *cbmem_top(void)
 {
 	return (void *) smm_region_start();