diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2016-06-09 18:13:34 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:48:44 +0200 |
| commit | 266a1f794dc28053e97794cbeb3f1a588137698b (patch) | |
| tree | 7cb11796fa351bd50d15af6be9508a15be223192 /src/northbridge/intel/nehalem | |
| parent | e7f35cd2924de7c9b2e8a74a50d35928b9da76a4 (diff) | |
nb/intel/raminit (native): Read PCI mmio size from devicetree
Instead of hardcoding the PCI mmio size read it from devicetree.
Set a default value of 2048 MiB and 1024MiB for laptops without
discrete graphics.
Tested on Sandybridge Lenovo T520.
Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/15140
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/nehalem')
| -rw-r--r-- | src/northbridge/intel/nehalem/chip.h | 5 | ||||
| -rw-r--r-- | src/northbridge/intel/nehalem/raminit.c | 26 |
2 files changed, 30 insertions, 1 deletions
diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index caf98196bd..a9d136baad 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -41,6 +41,11 @@ struct northbridge_intel_nehalem_config { u32 gpu_pch_backlight; /* PCH Backlight PWM value */ struct i915_gpu_controller_info gfx; + + /* + * Maximum PCI mmio size in MiB. + */ + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 0549de766a..69e7108271 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -32,10 +32,12 @@ #include <ip_checksum.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <device/device.h> #include <arch/cpu.h> #include <halt.h> #include <spd.h> #include "raminit.h" +#include "chip.h" #include <timestamp.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/speedstep.h> @@ -1450,6 +1452,25 @@ static void program_board_delay(struct raminfo *info) } } +#define DEFAULT_PCI_MMIO_SIZE 2048 +#define HOST_BRIDGE PCI_DEVFN(0, 0) + +static unsigned int get_mmio_size(void) +{ + const struct device *dev; + const struct northbridge_intel_nehalem_config *cfg = NULL; + + dev = dev_find_slot(0, HOST_BRIDGE); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + return DEFAULT_PCI_MMIO_SIZE; + else + return cfg->pci_mmio_size; +} + #define BETTER_MEMORY_MAP 0 static void program_total_memory_map(struct raminfo *info) @@ -1459,6 +1480,7 @@ static void program_total_memory_map(struct raminfo *info) unsigned int REMAPbase; unsigned int uma_base_igd; unsigned int uma_base_gtt; + unsigned int mmio_size; int memory_remap; unsigned int memory_map[8]; int i; @@ -1485,11 +1507,13 @@ static void program_total_memory_map(struct raminfo *info) } #endif + mmio_size = get_mmio_size(); + TOM = info->total_memory_mb; if (TOM == 4096) TOM = 4032; TOUUD = ALIGN_DOWN(TOM - info->memory_reserved_for_heci_mb, 64); - TOLUD = ALIGN_DOWN(min(3072 + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) + TOLUD = ALIGN_DOWN(min(4096 - mmio_size + ALIGN_UP(uma_size_igd + uma_size_gtt, 64) , TOUUD), 64); memory_remap = 0; if (TOUUD - TOLUD > 64) { |