nb/intel/nehalem: Add a header for raminit_tables.c

This is necessary to get rid of a .c include.

Also do some cosmetic fixes to a table, now that the line length limit
has been raised.

Change-Id: I6fd7fa5c9b21368bde8f089060733df6de34b4fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>

4 files changed, 86 insertions, 34 deletions

diff --git a/src/northbridge/intel/nehalem/Makefile.inc b/src/northbridge/intel/nehalem/Makefile.inc
index 52374acee8..ebb7b8be03 100644
--- a/src/northbridge/intel/nehalem/Makefile.inc
+++ b/src/northbridge/intel/nehalem/Makefile.inc
@@ -24,6 +24,7 @@ ramstage-y += acpi.c
 
 romstage-y += memmap.c
 romstage-y += raminit.c
+romstage-y += raminit_tables.c
 romstage-y += early_init.c
 romstage-y += ../../../arch/x86/walkcbfs.S
 
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index fadf0e0801..b9d407a58e 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -42,6 +42,7 @@
 #include "chip.h"
 #include "nehalem.h"
 #include "raminit.h"
+#include "raminit_tables.h"
 
 #define NORTHBRIDGE PCI_DEV(0, 0, 0)
 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
@@ -357,8 +358,6 @@ const int cached_config = 0;
 #define RANK_SHIFT 28
 #define CHANNEL_SHIFT 10
 
-#include "raminit_tables.c"
-
 static void seq9(struct raminfo *info, int channel, int slot, int rank)
 {
 	int i, lane;
diff --git a/src/northbridge/intel/nehalem/raminit_tables.c b/src/northbridge/intel/nehalem/raminit_tables.c
index 5c5d46f54a..1bd73305ea 100644
--- a/src/northbridge/intel/nehalem/raminit_tables.c
+++ b/src/northbridge/intel/nehalem/raminit_tables.c
@@ -14,6 +14,8 @@
  * GNU General Public License for more details.
  */
 
+#include "raminit_tables.h"
+
 /* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */
 const u8 u8_FFFD1240[2][5][9][4][4] = {
 	{
@@ -617,46 +619,30 @@ const u16 u16_ffd1188[2][9][4] = {
 const u8 u8_FFFD1891[2][2][4][12] = {
 	{
 	 {
-	  {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
+	  {0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x08, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00},
 	  },
 	 {
-	  {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
+	  {0x04, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x05, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x07, 0x00, 0x00, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x08, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00},
 	  }
 	 },
 	{
 	 {
-	  {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
+	  {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x0c, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00},
 	  },
 	 {
-	  {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00,
-	   0x00},
-	  {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	   0x74}
+	  {0x06, 0x00, 0x00, 0x08, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x08, 0x00, 0x00, 0x0a, 0x0a, 0x0a, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x0a, 0x00, 0x00, 0x0c, 0x0c, 0x0c, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00},
+	  {0x0c, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74}
 	  }
 	 }
 };
diff --git a/src/northbridge/intel/nehalem/raminit_tables.h b/src/northbridge/intel/nehalem/raminit_tables.h
new file mode 100644
index 0000000000..d912d6b18a
--- /dev/null
+++ b/src/northbridge/intel/nehalem/raminit_tables.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Vladimir Serbinenko.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef RAMINIT_TABLES_H
+#define RAMINIT_TABLES_H
+
+#include <types.h>
+
+/* [CHANNEL][EXT_REVISON][LANE][2*SLOT+RANK][CLOCK_SPEED] */
+extern const u8 u8_FFFD1240[2][5][9][4][4];
+
+extern const u16 u16_FFFE0EB8[2][4];
+
+/* [CARD][LANE][CLOCK_SPEED] */
+extern const u16 u16_ffd1188[2][9][4];
+
+/* [REVISION][CHANNEL][CLOCK_INDEX][?] */
+extern const u8 u8_FFFD1891[2][2][4][12];
+
+extern const u8 u8_FFFD17E0[2][5][4][4];
+
+extern const u8 u8_FFFD0C78[2][5][4][2][2][4];
+
+extern const u16 u16_fffd0c68[3];
+
+extern const u16 u16_fffd0c70[2][2];
+
+extern const u16 u16_fffd0c50[3][2][2];
+
+/* [CLOCK_INDEX] */
+extern const u16 min_cycletime[4];
+
+/* [CLOCK_INDEX] */
+extern const u16 min_cas_latency_time[4];
+
+/* [CHANNEL][EXT_SILICON_REVISION][?][CLOCK_INDEX] */
+/* On other mobos may also depend on slot and rank.  */
+extern const u8 u8_FFFD0EF8[2][5][4][4];
+
+/* [CLOCK_SPEED] */
+extern const u8 u8_FFFD1218[4];
+
+extern const u8 reg178_min[];
+extern const u8 reg178_max[];
+extern const u8 reg178_step[];
+
+extern const u16 u16_ffd1178[2][4];
+
+extern const u16 u16_fe0eb8[2][4];
+
+extern const u8 lut16[4];
+
+#endif // RAMINIT_TABLES_H