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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-02 06:14:50 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-07 05:31:35 +0000 |
commit | f6c20681d1d1fa66212ab58b6dc1e9112fe4651d (patch) | |
tree | a63e8691f768a193f64a9c5f2ad7ac952a6f876f /src/northbridge/intel/nehalem | |
parent | 0b7cc927b6b629072ba62f6fe3c01fc67ccf4ba1 (diff) |
intel/nehalem,sandybridge: Move stage_cache support function
Let garbage-collection take care of stage_cache_external_region()
if it is no needed and move implementation to a suitable file already
building for needed stages.
Remove aliasing CONFIG_RESERVED_SMM_SIZE as RESERVED_SMM_SIZE and
(unused) aliasing of CONFIG_IED_REGION_SIZE as IED_SIZE.
Change-Id: Idf00ba3180d8c3bc974dd3c5ca5f98a6c08bf34d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34672
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/nehalem')
-rw-r--r-- | src/northbridge/intel/nehalem/nehalem.h | 3 | ||||
-rw-r--r-- | src/northbridge/intel/nehalem/northbridge.c | 5 | ||||
-rw-r--r-- | src/northbridge/intel/nehalem/ram_calc.c | 15 |
3 files changed, 15 insertions, 8 deletions
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index b220c2d7a9..93024f69d8 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -122,9 +122,6 @@ typedef struct { #define IVB_STEP_K0 (BASE_REV_IVB + 5) #define IVB_STEP_D0 (BASE_REV_IVB + 6) -/* Intel Enhanced Debug region must be 4MB */ -#define IED_SIZE 0x400000 - /* Northbridge BARs */ #ifndef __ACPI__ #define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 485cb27f45..a058d3fa26 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -171,11 +171,6 @@ static void mc_read_resources(struct device *dev) add_fixed_resources(dev, 10); } -u32 northbridge_get_tseg_size(void) -{ - return CONFIG_SMM_TSEG_SIZE; -} - static void mc_set_resources(struct device *dev) { /* And call the normal set_resources */ diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index ba3761065b..ec036c9d7c 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,6 +23,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> +#include <stage_cache.h> #include <cpu/intel/smm/gen1/smi.h> #include "nehalem.h" @@ -38,11 +39,25 @@ u32 northbridge_get_tseg_base(void) return (u32)smm_region_start(); } +u32 northbridge_get_tseg_size(void) +{ + return CONFIG_SMM_TSEG_SIZE; +} + void *cbmem_top(void) { return (void *) smm_region_start(); } +void stage_cache_external_region(void **base, size_t *size) +{ + /* The stage cache lives at the end of TSEG region. + * The top of RAM is defined to be the TSEG base address. */ + *size = CONFIG_SMM_RESERVED_SIZE; + *base = (void *)((uintptr_t)northbridge_get_tseg_base() + + northbridge_get_tseg_size() - CONFIG_SMM_RESERVED_SIZE); +} + /* platform_enter_postcar() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use, * and continues execution in postcar stage. */ |