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authorElyes HAOUAS <ehaouas@noos.fr>2019-05-15 21:09:30 +0200
committerPatrick Georgi <pgeorgi@google.com>2019-05-29 20:28:27 +0000
commit51401c30509d189d07a8a94958bdecdfd8b7667d (patch)
tree97f7829ad4d84e19a069f93be56b369abb933e8d /src/northbridge/intel/nehalem
parent5fd93e05820d742fac5dbc1b371b464a88bb9043 (diff)
src/northbridge: Add missing 'include <types.h>'
<types.h> is supposed to provide <stdint.h> and <stddef.h>. When <types.h> is included, <stdint.h> and/or <stddef.h> is removed. Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32808 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Diffstat (limited to 'src/northbridge/intel/nehalem')
-rw-r--r--src/northbridge/intel/nehalem/gma.c1
-rw-r--r--src/northbridge/intel/nehalem/raminit.c10
2 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index 8c0117f531..087d37e5aa 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -31,6 +31,7 @@
#include <southbridge/intel/ibexpeak/nvs.h>
#include <drivers/intel/gma/opregion.h>
#include <cbmem.h>
+#include <types.h>
#include "chip.h"
#include "nehalem.h"
diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c
index 5b6077f5ea..15d6abb67b 100644
--- a/src/northbridge/intel/nehalem/raminit.c
+++ b/src/northbridge/intel/nehalem/raminit.c
@@ -30,18 +30,18 @@
#include <device/device.h>
#include <halt.h>
#include <spd.h>
-#include "raminit.h"
-#include "chip.h"
#include <timestamp.h>
#include <cpu/x86/mtrr.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <mrc_cache.h>
-
-#include "nehalem.h"
-
#include <southbridge/intel/ibexpeak/me.h>
#include <delay.h>
+#include <types.h>
+
+#include "chip.h"
+#include "nehalem.h"
+#include "raminit.h"
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)