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authorNico Huber <nico.h@gmx.de>2018-05-27 14:37:32 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-06-04 08:21:56 +0000
commit089b9089c111da9175d87c4f2671ba8ebe353b4b (patch)
treeba0def7c46a1cd0675334bda6ad1901e7992b412 /src/northbridge/intel/nehalem
parent36ec3e9ba1b89416d87426eabe496d67dbb2cdbf (diff)
nb/intel: Use postcar_frame_add_romcache()
Change-Id: I0729ca4cdad7d2218c1e1feae5cd38dda6d4e11e Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/26579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/northbridge/intel/nehalem')
-rw-r--r--src/northbridge/intel/nehalem/ram_calc.c3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c
index 93d1ccf125..bbf84f98d7 100644
--- a/src/northbridge/intel/nehalem/ram_calc.c
+++ b/src/northbridge/intel/nehalem/ram_calc.c
@@ -50,8 +50,7 @@ void *setup_stack_and_mtrrs(void)
die("Unable to initialize postcar frame.\n");
/* Cache the ROM as WP just below 4GiB. */
- postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
- MTRR_TYPE_WRPROT);
+ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
/* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */
postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK);