diff options
author | Angel Pons <th3fanbus@gmail.com> | 2020-02-17 13:08:53 +0100 |
---|---|---|
committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:04:20 +0000 |
commit | 95de2317c6c6379e43d3b3c27d34eb66198dbe0a (patch) | |
tree | e0df0c7dfce199b95609be41f0d806b5829d8005 /src/northbridge/intel/nehalem/smi.c | |
parent | 2aff3005e0ebdf99c0a0f063f023536f601a879b (diff) |
nb/intel/nehalem: Rename to ironlake
The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/nehalem/smi.c')
-rw-r--r-- | src/northbridge/intel/nehalem/smi.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/src/northbridge/intel/nehalem/smi.c b/src/northbridge/intel/nehalem/smi.c deleted file mode 100644 index c3433a39e7..0000000000 --- a/src/northbridge/intel/nehalem/smi.c +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define __SIMPLE_DEVICE__ - -#include <types.h> -#include <device/device.h> -#include <device/pci_ops.h> -#include "nehalem.h" - -#include <cpu/intel/smm_reloc.h> - -void northbridge_write_smram(u8 smram) -{ - pci_write_config8(PCI_DEV(QUICKPATH_BUS, 0, 1), QPD0F1_SMRAM, smram); -} |