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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-05 07:54:28 +0200
committerNico Huber <nico.h@gmx.de>2019-03-06 11:54:17 +0000
commit503d3247e48d803ce36e98d2064cf22220bb0dfd (patch)
treef50d79bf985fdcf6489178ffdc9918d1f0759183 /src/northbridge/intel/nehalem/nehalem.h
parente079e5ccc2e707e5b6bd3b011e04c9138f159808 (diff)
Remove DEFAULT_PCIEXBAR alias
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/nehalem/nehalem.h')
-rw-r--r--src/northbridge/intel/nehalem/nehalem.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h
index 1f686d57b2..b220c2d7a9 100644
--- a/src/northbridge/intel/nehalem/nehalem.h
+++ b/src/northbridge/intel/nehalem/nehalem.h
@@ -52,8 +52,6 @@ typedef struct {
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
- /* 4 KB per PCIe device */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
@@ -128,7 +126,6 @@ typedef struct {
#define IED_SIZE 0x400000
/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed10000) /* 16 KB */
#define DEFAULT_DMIBAR ((u8 *)0xfed18000) /* 4 KB */