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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:41:06 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:32:10 +0000
commitdddd1cc6913bd0cbb814b68de7315cb84bfb9c2f (patch)
treee4ad63b1db7fbeaf14ad5bf60046a0ed063b86a5 /src/northbridge/intel/ironlake
parent7aa3372ce21565962d4cb1090e1f194b6f33f968 (diff)
src/northbridge: Drop unneeded empty lines
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake')
-rw-r--r--src/northbridge/intel/ironlake/ironlake.h2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h
index aa9a8b7605..7ed6afde3e 100644
--- a/src/northbridge/intel/ironlake/ironlake.h
+++ b/src/northbridge/intel/ironlake/ironlake.h
@@ -5,7 +5,6 @@
#define DEFAULT_HECIBAR ((u8 *)0xfed17000)
-
#define IOMMU_BASE1 0xfed90000
#define IOMMU_BASE2 0xfed91000
#define IOMMU_BASE3 0xfed92000
@@ -93,7 +92,6 @@
#define QPI_PHY_EP_SELECT 0xe0 /* QPI Phys. Layer Electrical Parameter Select */
#define QPI_PHY_EP_MCTR 0xf4 /* QPI Phys. Layer Electrical Parameter Misc. Control */
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */