diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-22 18:11:31 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-02 19:29:10 +0000 |
| commit | 43bcc7b6ed1502de80a857f94443f7c83269ad36 (patch) | |
| tree | 90339cc8e0aa32d51be79af708c626552bd8ec07 /src/northbridge/intel/ironlake/romstage.c | |
| parent | aee3b148ba8263e983de12cfb873ee5ec6d0569f (diff) | |
nb/intel/ironlake: Clean up code style (except raminit)
Reflow lines, correct coding style and align struct members, among
other things. As raminit is very large, handle it on a follow-up.
Tested with BUILD_TIMELESS=1, packardbell/ms2290 does not change.
Change-Id: I343edf1bc2a5ac20ff0aa6de4486e685ce430737
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42701
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake/romstage.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/romstage.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/northbridge/intel/ironlake/romstage.c b/src/northbridge/intel/ironlake/romstage.c index 4a335d853c..e5ecafe2a2 100644 --- a/src/northbridge/intel/ironlake/romstage.c +++ b/src/northbridge/intel/ironlake/romstage.c @@ -17,7 +17,8 @@ #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/ibexpeak/me.h> -/* Platform has no romstage entry point under mainboard directory, +/* + * Platform has no romstage entry point under mainboard directory, * so this one is named with prefix mainboard. */ void mainboard_romstage_entry(void) @@ -59,7 +60,8 @@ void mainboard_romstage_entry(void) intel_early_me_status(); if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but + /* + * Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ reg32 = inl(DEFAULT_PMBASE + 0x04); |