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| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:12:33 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:28:57 +0000 |
| commit | 16fe1e0246df10fd9bac30c091b38d454d96cc89 (patch) | |
| tree | 2b3f3118e9e0e4308f1420b5a465c9b8290b519a /src/northbridge/intel/ironlake/northbridge.c | |
| parent | 9333b742295a1e8eb630b2e73fcac43318e10b6a (diff) | |
nb/intel/ironlake: Drop `D0F0_` prefix from register names
Only some registers have such a prefix. Drop it for consistency.
Change-Id: I1ef7307d10a06db8f3c1a05bd9184f21fceb9d90
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/northbridge.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index 4cd098ce92..b99e2d5b43 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -103,7 +103,7 @@ static void mc_read_resources(struct device *dev) tseg_base = pci_read_config32(pcidev_on_root(0, 0), TSEG); touud = pci_read_config16(pcidev_on_root(0, 0), - D0F0_TOUUD); + TOUUD); printk(BIOS_DEBUG, "ram_before_4g_top: 0x%x\n", tseg_base); printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud); @@ -114,7 +114,7 @@ static void mc_read_resources(struct device *dev) mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); - reg16 = pci_read_config16(pcidev_on_root(0, 0), D0F0_GGC); + reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC); const int uma_sizes_gtt[16] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4, 42, 42, 42, 42 }; /* Igd memory */ @@ -128,9 +128,9 @@ static void mc_read_resources(struct device *dev) uma_size_gtt = uma_sizes_gtt[(reg16 >> 8) & 0xF]; igd_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_IGD_BASE); + pci_read_config32(pcidev_on_root(0, 0), IGD_BASE); gtt_base = - pci_read_config32(pcidev_on_root(0, 0), D0F0_GTT_BASE); + pci_read_config32(pcidev_on_root(0, 0), GTT_BASE); mmio_resource(dev, 6, gtt_base >> 10, uma_size_gtt << 10); mmio_resource(dev, 7, igd_base >> 10, uma_size_igd << 10); @@ -183,7 +183,7 @@ static void ironlake_init(void *const chip_info) } const struct device *const d0f0 = pcidev_on_root(0, 0); if (d0f0) - pci_update_config32(d0f0, D0F0_DEVEN, deven_mask, 0); + pci_update_config32(d0f0, DEVEN, deven_mask, 0); } |