diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:56:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:31:11 +0000 |
| commit | 67573371d5ade1ad388316585901ee9d0edfe512 (patch) | |
| tree | c925a49f9a2dcda5ad0ab1b828054ecf409ec00f /src/northbridge/intel/ironlake/ironlake.h | |
| parent | 45008930626bda902c8f37880e6f09d517b8cdd2 (diff) | |
nb/intel/ironlake: Add SAD DRAM register definitions
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: I66b87d15f6b741c6fc935106c35b201fbd9ab2c6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/ironlake.h')
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index afd30823d5..fa59565ba8 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -57,6 +57,9 @@ #define SAD_PCIEXBAR 0x50 +#define SAD_DRAM_RULE(x) (0x80 + 4 * (x)) /* 0-7 */ +#define SAD_INTERLEAVE_LIST(x) (0xc0 + 4 * (x)) /* 0-7 */ + /* Device 0:2.0 PCI configuration space (Graphics Device) */ |