diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:43:48 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:30:59 +0000 |
| commit | 45008930626bda902c8f37880e6f09d517b8cdd2 (patch) | |
| tree | be885c8deea5a176a9f0423b25a239df98ad7f8d /src/northbridge/intel/ironlake/ironlake.h | |
| parent | 3ab19b32a2d417a03e2b3d9942eae981dd951233 (diff) | |
nb/intel/ironlake: Correct PCIEXBAR definition
This register resides within the SAD's config space, and is 64-bit.
Change-Id: I19458f7c6be6b1a5fcd47ac93ee0597f1251a770
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/ironlake.h')
| -rw-r--r-- | src/northbridge/intel/ironlake/ironlake.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/ironlake.h b/src/northbridge/intel/ironlake/ironlake.h index dd8de97f0a..afd30823d5 100644 --- a/src/northbridge/intel/ironlake/ironlake.h +++ b/src/northbridge/intel/ironlake/ironlake.h @@ -55,6 +55,8 @@ #define QPD0F1_PAM(x) (0x40 + (x)) /* 0-6 */ #define QPD0F1_SMRAM 0x4d /* System Management RAM Control */ +#define SAD_PCIEXBAR 0x50 + /* Device 0:2.0 PCI configuration space (Graphics Device) */ |