diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 01:32:17 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-10 07:29:29 +0000 |
| commit | a8df6cff16d4f24a7f6dfedd5979d0948ddda189 (patch) | |
| tree | 949d112b6fb9ec868200dfb57869d2f3b0fb6b59 /src/northbridge/intel/ironlake/early_init.c | |
| parent | d9e58dca9e72ca2efa62eab832aad606c9c58fcd (diff) | |
nb/intel/ironlake: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical.
Change-Id: I166dbebf0eaf9fe0454145d4d48a0622743916fd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/ironlake/early_init.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index e0120fe078..767db0d3ba 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -17,12 +17,12 @@ static void ironlake_setup_bars(void) { printk(BIOS_DEBUG, "Setting up static northbridge registers..."); /* Set up all hardcoded northbridge BARs */ - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, 0); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); + pci_write_config32(PCI_DEV(0, 0, 0), EPBAR, CONFIG_FIXED_EPBAR_MMIO_BASE | 1); + pci_write_config32(PCI_DEV(0, 0, 0), EPBAR + 4, 0); + pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR, CONFIG_FIXED_MCHBAR_MMIO_BASE | 1); + pci_write_config32(PCI_DEV(0, 0, 0), MCHBAR + 4, 0); + pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR, CONFIG_FIXED_DMIBAR_MMIO_BASE | 1); + pci_write_config32(PCI_DEV(0, 0, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); |