diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-22 16:29:54 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-08-03 05:30:50 +0000 |
| commit | 3ab19b32a2d417a03e2b3d9942eae981dd951233 (patch) | |
| tree | dc5c5044388a287b9ece26cf9a97a6bac2ef1f8b /src/northbridge/intel/ironlake/early_init.c | |
| parent | 16fe1e0246df10fd9bac30c091b38d454d96cc89 (diff) | |
nb/intel/ironlake: Add definition for SAD PCI device
Let's hope this cheers up the poor System Address Decoder device.
Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.
Change-Id: Ia62c05abb07216dc1ba449c3a17f8d53050b5af1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43732
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/ironlake/early_init.c')
| -rw-r--r-- | src/northbridge/intel/ironlake/early_init.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/ironlake/early_init.c b/src/northbridge/intel/ironlake/early_init.c index b68d954849..2154478bdb 100644 --- a/src/northbridge/intel/ironlake/early_init.c +++ b/src/northbridge/intel/ironlake/early_init.c @@ -25,13 +25,13 @@ static void ironlake_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, 0); /* Set C0000-FFFFF to access RAM on both reads and writes */ - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(0), 0x30); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(1), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(2), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(3), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(4), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(5), 0x33); - pci_write_config8(PCI_DEV(0xff, 0x00, 1), QPD0F1_PAM(6), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(0), 0x30); + pci_write_config8(QPI_SAD, QPD0F1_PAM(1), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(2), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(3), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(4), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(5), 0x33); + pci_write_config8(QPI_SAD, QPD0F1_PAM(6), 0x33); printk(BIOS_DEBUG, " done.\n"); } |