diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-02-17 13:08:53 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 13:04:20 +0000 |
| commit | 95de2317c6c6379e43d3b3c27d34eb66198dbe0a (patch) | |
| tree | e0df0c7dfce199b95609be41f0d806b5829d8005 /src/northbridge/intel/ironlake/Kconfig | |
| parent | 2aff3005e0ebdf99c0a0f063f023536f601a879b (diff) | |
nb/intel/nehalem: Rename to ironlake
The code is for Arrandale CPUs, whose System Agent is Ironlake.
This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.
Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.
Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/ironlake/Kconfig')
| -rw-r--r-- | src/northbridge/intel/ironlake/Kconfig | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig new file mode 100644 index 0000000000..512149bfee --- /dev/null +++ b/src/northbridge/intel/ironlake/Kconfig @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config NORTHBRIDGE_INTEL_IRONLAKE + bool + select CPU_INTEL_MODEL_2065X + select VGA + select INTEL_EDID + select INTEL_GMA_ACPI + select CACHE_MRC_SETTINGS + select HAVE_DEBUG_RAM_SETUP + +if NORTHBRIDGE_INTEL_IRONLAKE + +config VBOOT + select VBOOT_MUST_REQUEST_DISPLAY + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + # CPU is reset without platform/TPM during romstage + select TPM_STARTUP_IGNORE_POSTINIT + +config MMCONF_BUS_NUMBER + int + default 256 + +config CBFS_SIZE + hex + default 0x100000 + +config VGA_BIOS_ID + string + default "8086,0046" + +config DCACHE_RAM_BASE + hex + default 0xfefc0000 + +config DCACHE_RAM_SIZE + hex + default 0x10000 + +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +endif |