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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-07-05 18:05:17 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-09-24 22:56:52 +0000
commite39becf5216419fa0a08c1d8632474fd8a9a5738 (patch)
treee4baed9dcf299738c09930d12421672b0133c478 /src/northbridge/intel/i945
parentc00e2fb9966a9c4bd30944a198ad036ee81a2b0d (diff)
intel/cpu: Switch older models to TSC_MONOTONIC_TIMER
The implementation of udelay() with LAPIC timers existed first, as we did not have calculations implemented for TSC frequency. Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945')
-rw-r--r--src/northbridge/intel/i945/Kconfig1
-rw-r--r--src/northbridge/intel/i945/Makefile.inc2
-rw-r--r--src/northbridge/intel/i945/udelay.c77
3 files changed, 0 insertions, 80 deletions
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index 1edd0eadf9..0159bf2fde 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
def_bool y
select HAVE_DEBUG_RAM_SETUP
- select LAPIC_MONOTONIC_TIMER
select VGA
select INTEL_GMA_ACPI
select INTEL_GMA_SSC_ALTERNATE_REF
diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc
index 47b4c5166b..af3c23580c 100644
--- a/src/northbridge/intel/i945/Makefile.inc
+++ b/src/northbridge/intel/i945/Makefile.inc
@@ -27,8 +27,6 @@ romstage-y += errata.c
romstage-y += debug.c
romstage-y += rcven.c
-smm-y += udelay.c
-
postcar-y += memmap.c
endif
diff --git a/src/northbridge/intel/i945/udelay.c b/src/northbridge/intel/i945/udelay.c
deleted file mode 100644
index 8447453435..0000000000
--- a/src/northbridge/intel/i945/udelay.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-#include <stdint.h>
-#include <cpu/x86/tsc.h>
-#include <cpu/x86/msr.h>
-#include <cpu/intel/speedstep.h>
-
-/**
- * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock
- */
-
-void udelay(u32 us)
-{
- u32 dword;
- tsc_t tsc, tsc1, tscd;
- msr_t msr;
- u32 fsb = 0, divisor;
- u32 d; /* ticks per us */
-
- msr = rdmsr(MSR_FSB_FREQ);
- switch (msr.lo & 0x07) {
- case 5:
- fsb = 400;
- break;
- case 1:
- fsb = 533;
- break;
- case 3:
- fsb = 667;
- break;
- case 2:
- fsb = 800;
- break;
- case 0:
- fsb = 1067;
- break;
- case 4:
- fsb = 1333;
- break;
- case 6:
- fsb = 1600;
- break;
- }
-
- msr = rdmsr(IA32_PERF_STATUS);
- divisor = (msr.hi >> 8) & 0x1f;
-
- d = (fsb * divisor) / 4; /* CPU clock is always a quarter. */
-
- multiply_to_tsc(&tscd, us, d);
-
- tsc1 = rdtsc();
- dword = tsc1.lo + tscd.lo;
- if ((dword < tsc1.lo) || (dword < tscd.lo))
- tsc1.hi++;
- tsc1.lo = dword;
- tsc1.hi += tscd.hi;
-
- do {
- tsc = rdtsc();
- } while ((tsc.hi < tsc1.hi)
- || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo)));
-}