printk_foo -> printk(BIOS_FOO, ...)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

5 files changed, 207 insertions, 209 deletions

diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 4a59fee372..a14d0cec63 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -36,9 +36,9 @@ static void print_pci_devices(void)
 			(((id >> 16) & 0xffff) == 0x0000)) {
 			continue;
 		}
-		printk_debug("PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
+		printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev >> 20) & 0xff,
 			(dev >> 15) & 0x1f, (dev >> 12) & 7);
-		printk_debug(" [%04x:%04x]\n", id &0xffff, id >> 16);
+		printk(BIOS_DEBUG, " [%04x:%04x]\n", id &0xffff, id >> 16);
 	}
 }
 
@@ -46,17 +46,17 @@ static void dump_pci_device(unsigned dev)
 {
 	int i;
 
-	printk_debug("PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
+	printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
 
 	for(i = 0; i <= 255; i++) {
 		unsigned char val;
 		if ((i & 0x0f) == 0) {
-			printk_debug("%02x:", i);
+			printk(BIOS_DEBUG, "%02x:", i);
 		}
 		val = pci_read_config8(dev, i);
-		printk_debug(" %02x", val);
+		printk(BIOS_DEBUG, " %02x", val);
 		if ((i & 0x0f) == 0x0f) {
-			printk_debug("\n");
+			printk(BIOS_DEBUG, "\n");
 		}
 	}
 }
@@ -85,21 +85,21 @@ void dump_spd_registers(void)
         while(device <= SMBUS_MEM_DEVICE_END) {
                 int status = 0;
                 int i;
-        	printk_debug("\ndimm %02x", device);
+        	printk(BIOS_DEBUG, "\ndimm %02x", device);
 		
                 for(i = 0; (i < 256) ; i++) {
                         if ((i % 16) == 0) {
-				printk_debug("\n%02x: ", i);
+				printk(BIOS_DEBUG, "\n%02x: ", i);
                         }
 			status = smbus_read_byte(device, i);
                         if (status < 0) {
-			         printk_debug("bad device: %02x\n", -status);
+			         printk(BIOS_DEBUG, "bad device: %02x\n", -status);
 			         break; 
 			}
-			printk_debug("%02x ", status);
+			printk(BIOS_DEBUG, "%02x ", status);
 		}
 		device += SMBUS_MEM_DEVICE_INC;
-		printk_debug("\n");
+		printk(BIOS_DEBUG, "\n");
 	}
 }
 
@@ -109,9 +109,9 @@ static void dump_mem(unsigned start, unsigned end)
 	print_debug("dump_mem:");
         for(i=start;i<end;i++) {
 		if((i & 0xf)==0) {
-			printk_debug("\n%08x:", i);
+			printk(BIOS_DEBUG, "\n%08x:", i);
 		}
-		printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+		printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
         }
         print_debug("\n");
  }
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index d16f77a349..f6cdcca961 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -29,108 +29,108 @@ static void i945m_detect_chipset(void)
 {
 	u8 reg8;
 
-	printk_info("\n");
+	printk(BIOS_INFO, "\n");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) & 0x70) >> 4;
 	switch (reg8) {
 	case 1:
-		printk_info("Mobile Intel(R) 82945GM/GME Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GM/GME Express");
 		break;
 	case 2:
-		printk_info("Mobile Intel(R) 82945GMS/GU Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945GMS/GU Express");
 		break;
 	case 3:
-		printk_info("Mobile Intel(R) 82945PM Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82945PM Express");
 		break;
 	case 5:
-		printk_info("Intel(R) 82945GT Express");
+		printk(BIOS_INFO, "Intel(R) 82945GT Express");
 		break;
 	case 6:
-		printk_info("Mobile Intel(R) 82943/82940GML Express");
+		printk(BIOS_INFO, "Mobile Intel(R) 82943/82940GML Express");
 		break;
 	default:
-		printk_info("Unknown (%02x)", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "Unknown (%02x)", reg8);	/* Others reserved. */
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of up to FSB ");
+	printk(BIOS_DEBUG, "(G)MCH capable of up to FSB ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe3) & 0xe0) >> 5;
 	switch (reg8) {
 	case 2:
-		printk_debug("800 MHz"); /* According to 965 spec */
+		printk(BIOS_DEBUG, "800 MHz"); /* According to 965 spec */
 		break;
 	case 3:
-		printk_debug("667 MHz");
+		printk(BIOS_DEBUG, "667 MHz");
 		break;
 	case 4:
-		printk_debug("533 MHz");
+		printk(BIOS_DEBUG, "533 MHz");
 		break;
 	default:
-		printk_debug("N/A MHz (%02x)", reg8);
+		printk(BIOS_DEBUG, "N/A MHz (%02x)", reg8);
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 2:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	case 4:
-		printk_debug("DDR2-400");
+		printk(BIOS_DEBUG, "DDR2-400");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_detect_chipset(void)
 {
 	u8 reg8;
 
-	printk_info("\nIntel(R) ");
+	printk(BIOS_INFO, "\nIntel(R) ");
 
 	reg8 = ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe7) >> 5) & 4) | ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) >> 4) & 3);
 	switch (reg8) {
 	case 0:
 	case 1:
-		printk_info("82945G");
+		printk(BIOS_INFO, "82945G");
 		break;
 	case 2:
 	case 3:
-		printk_info("82945P");
+		printk(BIOS_INFO, "82945P");
 		break;
 	case 4:
-		printk_info("82945GC");
+		printk(BIOS_INFO, "82945GC");
 		break;
 	case 5:
-		printk_info("82945GZ");
+		printk(BIOS_INFO, "82945GZ");
 		break;
 	case 6:
 	case 7:
-		printk_info("82945PL");
+		printk(BIOS_INFO, "82945PL");
 		break;
 	default:
 		break;
 	}
-	printk_info(" Chipset\n");
+	printk(BIOS_INFO, " Chipset\n");
 
-	printk_debug("(G)MCH capable of ");
+	printk(BIOS_DEBUG, "(G)MCH capable of ");
 	reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07);
 	switch (reg8) {
 	case 0:
-		printk_debug("up to DDR2-667");
+		printk(BIOS_DEBUG, "up to DDR2-667");
 		break;
 	case 3:
-		printk_debug("up to DDR2-533");
+		printk(BIOS_DEBUG, "up to DDR2-533");
 		break;
 	default:
-		printk_info("unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
+		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
-	printk_debug("\n");
+	printk(BIOS_DEBUG, "\n");
 }
 
 static void i945_setup_bars(void)
@@ -139,11 +139,10 @@ static void i945_setup_bars(void)
 
 	/* As of now, we don't have all the A0 workarounds implemented */
 	if (i945_silicon_revision() == 0)
-		printk_info
-		    ("Warning: i945 silicon revision A0 might not work correctly.\n");
+		printk(BIOS_INFO, "Warning: i945 silicon revision A0 might not work correctly.\n");
 
 	/* Setting up Southbridge. In the northbridge code. */
-	printk_debug("Setting up static southbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
@@ -152,14 +151,14 @@ static void i945_setup_bars(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
 	setup_ich7_gpios();
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Disabling Watchdog reboot...");
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
 	RCBA32(GCS) = (RCBA32(0x3410)) | (1 << 5);	/* No reset */
 	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
-	printk_debug("Setting up static northbridge registers...");
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
 	/* Set up all hardcoded northbridge BARs */
 	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
 	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
@@ -182,16 +181,16 @@ static void i945_setup_bars(void)
 	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
 
 	pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
-	printk_debug(" done.\n");
+	printk(BIOS_DEBUG, " done.\n");
 
 	/* Wait for MCH BAR to come up */
-	printk_debug("Waiting for MCHBAR to come up...");
+	printk(BIOS_DEBUG, "Waiting for MCHBAR to come up...");
 	if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */
 		do {
 			reg8 = *(volatile u8 *)0xfed40000;
 		} while (!(reg8 & 0x80));
 	}
-	printk_debug("ok\n");
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void i945_setup_egress_port(void)
@@ -199,7 +198,7 @@ static void i945_setup_egress_port(void)
 	u32 reg32;
 	u32 timeout;
 
-	printk_debug("Setting up Egress Port RCRB\n");
+	printk(BIOS_DEBUG, "Setting up Egress Port RCRB\n");
 
 	/* Egress Port Virtual Channel 0 Configuration */
 
@@ -267,26 +266,26 @@ static void i945_setup_egress_port(void)
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 	EPBAR32(EPVC1RCTL) |= (1 << 16);
 
-	printk_debug("Loading port arbitration table ...");
+	printk(BIOS_DEBUG, "Loading port arbitration table ...");
 	/* Loop until bit 0 becomes 0 */
 	timeout = 0x7fffff;
 	while ((EPBAR16(EPVC1RSTS) & 1) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Now enable VC1 */
 	EPBAR32(EPVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7fff;
 	while ((EPBAR16(EPVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 }
 
@@ -348,7 +347,7 @@ static void i945_setup_dmi_rcrb(void)
 
 	int activate_aspm = 1;
 
-	printk_debug("Setting up DMI RCRB\n");
+	printk(BIOS_DEBUG, "Setting up DMI RCRB\n");
 
 	/* Virtual Channel 0 Configuration */
 	reg32 = DMIBAR32(DMIVC0RCTL0);
@@ -373,14 +372,14 @@ static void i945_setup_dmi_rcrb(void)
 	/* Now enable VC1 */
 	DMIBAR32(DMIVC1RCTL) |= (1 << 31);
 
-	printk_debug("Wait for VC1 negotiation ...");
+	printk(BIOS_DEBUG, "Wait for VC1 negotiation ...");
 	/* Wait for VC1 negotiation pending */
 	timeout = 0x7ffff;
 	while ((DMIBAR16(DMIVC1RSTS) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("done..\n");
+		printk(BIOS_DEBUG, "done..\n");
 #if 1
 	/* Enable Active State Power Management (ASPM) L0 state */
 
@@ -425,10 +424,10 @@ static void i945_setup_dmi_rcrb(void)
 	DMIBAR32(0x204) = reg32;
 
 	if (pci_read_config8(PCI_DEV(0, 0x0, 0), 0x54) & ((1 << 4) | (1 << 3))) {	/* DEVEN */
-		printk_debug("Internal graphics: enabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: enabled\n");
 		DMIBAR32(0x200) |= (1 << 21);
 	} else {
-		printk_debug("Internal graphics: disabled\n");
+		printk(BIOS_DEBUG, "Internal graphics: disabled\n");
 		DMIBAR32(0x200) &= ~(1 << 21);
 	}
 
@@ -474,13 +473,13 @@ static void i945_setup_dmi_rcrb(void)
 	}
 
 	/* wait for bit toggle to 0 */
-	printk_debug("Waiting for DMI hardware...");
+	printk(BIOS_DEBUG, "Waiting for DMI hardware...");
 	timeout = 0x7fffff;
 	while ((DMIBAR8(0x32) & (1 << 1)) && --timeout) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	DMIBAR32(0x1c4) = 0xffffffff;
 	DMIBAR32(0x1d0) = 0xffffffff;
@@ -495,8 +494,7 @@ static void i945_setup_dmi_rcrb(void)
 
 	if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) {
 		if ((MCHBAR32(0x214) & 0xf) != 0x3) {
-			printk_info
-			    ("DMI link requires A1 stepping workaround. Rebooting.\n");
+			printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n");
 			reg32 = DMIBAR32(0x224);
 			reg32 &= ~(7 << 0);
 			reg32 |= (3 << 0);
@@ -515,7 +513,7 @@ static void i945_setup_pci_express_x16(void)
 
 	u8 reg8;
 
-	printk_debug("Enabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Enabling PCI Express x16 Link\n");
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
 	reg16 |= DEVEN_D1F0;
@@ -540,7 +538,7 @@ static void i945_setup_pci_express_x16(void)
 	pci_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
 	reg16 = pci_read_config16(PCI_DEV(0, 0x01, 0), 0xba);
-	printk_debug("SLOTSTS: %04x\n", reg16);
+	printk(BIOS_DEBUG, "SLOTSTS: %04x\n", reg16);
 	if (!(reg16 & 0x48)) {
 		goto disable_pciexpress_x16_link;
 	}
@@ -576,18 +574,18 @@ static void i945_setup_pci_express_x16(void)
 	pcie_write_config32(PCI_DEV(0, 0x01, 0), 0xb4, reg32);
 
 	/* Wait for training to succeed */
-	printk_debug("PCIe link training ...");
+	printk(BIOS_DEBUG, "PCIe link training ...");
 	timeout = 0x7ffff;
 	while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 	reg32 = pci_read_config32(PCI_DEV(0x0a, 0x0, 0), 0);
 	if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-		printk_debug(" Detected PCIe device %04x:%04x\n",
+		printk(BIOS_DEBUG, " Detected PCIe device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 	} else {
-		printk_debug(" timeout!\n");
+		printk(BIOS_DEBUG, " timeout!\n");
 
-		printk_debug("Restrain PCIe port to x1\n");
+		printk(BIOS_DEBUG, "Restrain PCIe port to x1\n");
 
 		reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 		reg32 &= ~(0xf << 1);
@@ -601,17 +599,17 @@ static void i945_setup_pci_express_x16(void)
 		reg16 &= ~(1 << 6);
 		pcie_write_config16(PCI_DEV(0, 0x01, 0), 0x3e, reg16);
 
-		printk_debug("PCIe link training ...");
+		printk(BIOS_DEBUG, "PCIe link training ...");
 		timeout = 0x7ffff;
 		while ((((pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214) >> 16) & 4) != 3)  && --timeout) ;
 
 		reg32 = pci_read_config32(PCI_DEV(0xa, 0x00, 0), 0);
 		if (reg32 != 0x00000000 && reg32 != 0xffffffff) {
-			printk_debug(" Detected PCIe x1 device %04x:%04x\n",
+			printk(BIOS_DEBUG, " Detected PCIe x1 device %04x:%04x\n",
 				reg32 & 0xffff, reg32 >> 16);
 		} else {
-			printk_debug(" timeout!\n");
-			printk_debug("Disabling PCIe x16 port completely.\n");
+			printk(BIOS_DEBUG, " timeout!\n");
+			printk(BIOS_DEBUG, "Disabling PCIe x16 port completely.\n");
 			goto disable_pciexpress_x16_link;
 		}
 	}
@@ -620,7 +618,7 @@ static void i945_setup_pci_express_x16(void)
 	reg16 >>= 4;
 	reg16 &= 0x3f;
 	/* reg16 == 1 -> x1; reg16 == 16 -> x16 */
-	printk_debug("PCIe x%d link training succeeded.\n", reg16);
+	printk(BIOS_DEBUG, "PCIe x%d link training succeeded.\n", reg16);
 
 	reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x204);
 	reg32 &= 0xfffffc00; /* clear [9:0] */
@@ -633,9 +631,9 @@ static void i945_setup_pci_express_x16(void)
 	}
 
 	reg32 = (pci_read_config32(PCI_DEV(0xa, 0, 0), 0x8) >> 8);
-	printk_debug("PCIe device class: %06x\n", reg32);
+	printk(BIOS_DEBUG, "PCIe device class: %06x\n", reg32);
 	if (reg32 == 0x030000) {
-		printk_debug("PCIe device is VGA. Disabling IGD.\n");
+		printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n");
 		reg16 = (1 << 1);
 		pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16);
 
@@ -758,7 +756,7 @@ static void i945_setup_pci_express_x16(void)
 
 disable_pciexpress_x16_link:
 	/* For now we just disable the x16 link */
-	printk_debug("Disabling PCI Express x16 Link\n");
+	printk(BIOS_DEBUG, "Disabling PCI Express x16 Link\n");
 
 	MCHBAR16(UPMC1) |= (1 << 5) | (1 << 0);
 
@@ -774,14 +772,14 @@ disable_pciexpress_x16_link:
 	reg16 &= ~(1 << 6);
 	pcie_write_config16(PCI_DEV(0, 0x01, 0), BCTRL1, reg16);
 
-	printk_debug("Wait for link to enter detect state... ");
+	printk(BIOS_DEBUG, "Wait for link to enter detect state... ");
 	timeout = 0x7fffff;
 	for (reg32 = pcie_read_config32(PCI_DEV(0, 0x01, 0), 0x214);
 	     (reg32 & 0x000f0000) && --timeout;) ;
 	if (!timeout)
-		printk_debug("timeout!\n");
+		printk(BIOS_DEBUG, "timeout!\n");
 	else
-		printk_debug("ok\n");
+		printk(BIOS_DEBUG, "ok\n");
 
 	/* Finally: Disable the PCI config header */
 	reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), DEVEN);
@@ -793,7 +791,7 @@ static void i945_setup_root_complex_topology(void)
 {
 	u32 reg32;
 
-	printk_debug("Setting up Root Complex Topology\n");
+	printk(BIOS_DEBUG, "Setting up Root Complex Topology\n");
 	/* Egress Port Root Topology */
 
 	reg32 = EPBAR32(EPESD);
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 5f71e19a90..1f5a0359c4 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -75,11 +75,11 @@ int add_northbridge_resources(struct lb_memory *mem)
 {
 	u32 pcie_config_base, pcie_config_size;
 
-	printk_debug("Adding UMA memory area\n");
+	printk(BIOS_DEBUG, "Adding UMA memory area\n");
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		uma_memory_base, uma_memory_size);
 
-	printk_debug("Adding PCIe config bar\n");
+	printk(BIOS_DEBUG, "Adding PCIe config bar\n");
 	get_pcie_bar(&pcie_config_base, &pcie_config_size);
 	lb_add_memory_range(mem, LB_MEM_RESERVED,
 		pcie_config_base, pcie_config_size);
@@ -140,13 +140,13 @@ static void pci_domain_set_resources(device_t dev)
 	 * this way?
 	 */
 	pci_tolm = find_pci_tolm(&dev->link[0]);
-	printk_debug("pci_tolm: 0x%x\n", pci_tolm);
+	printk(BIOS_DEBUG, "pci_tolm: 0x%x\n", pci_tolm);
 
-	printk_spew("Base of stolen memory: 0x%08x\n",
+	printk(BIOS_SPEW, "Base of stolen memory: 0x%08x\n",
 		    pci_read_config32(dev_find_slot(0, PCI_DEVFN(2, 0)), 0x5c));
 
 	tolud = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9c);
-	printk_spew("Top of Low Used DRAM: 0x%08x\n", tolud << 24);
+	printk(BIOS_SPEW, "Top of Low Used DRAM: 0x%08x\n", tolud << 24);
 
 	tomk = tolud << 14;
 
@@ -154,7 +154,7 @@ static void pci_domain_set_resources(device_t dev)
 	reg8 = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), 0x9e);
 	if (reg8 & 1) {
 		int tseg_size = 0;
-		printk_debug("TSEG decoded, subtracting ");
+		printk(BIOS_DEBUG, "TSEG decoded, subtracting ");
 		reg8 >>= 1;
 		reg8 &= 3;
 		switch (reg8) {
@@ -169,14 +169,14 @@ static void pci_domain_set_resources(device_t dev)
 			break;	/* TSEG = 8M */
 		}
 
-		printk_debug("%dM\n", tseg_size >> 10);
+		printk(BIOS_DEBUG, "%dM\n", tseg_size >> 10);
 		tomk -= tseg_size;
 	}
 
 	reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), GGC);
 	if (!(reg16 & 2)) {
 		int uma_size = 0;
-		printk_debug("IGD decoded, subtracting ");
+		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
 		reg16 >>= 4;
 		reg16 &= 7;
 		switch (reg16) {
@@ -188,7 +188,7 @@ static void pci_domain_set_resources(device_t dev)
 			break;
 		}
 
-		printk_debug("%dM UMA\n", uma_size >> 10);
+		printk(BIOS_DEBUG, "%dM UMA\n", uma_size >> 10);
 		tomk -= uma_size;
 
 		/* For reserving UMA memory in the memory map */
@@ -199,8 +199,8 @@ static void pci_domain_set_resources(device_t dev)
 	/* The following needs to be 2 lines, otherwise the second
 	 * number is always 0
 	 */
-	printk_info("Available memory: %dK", (uint32_t)tomk);
-	printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
+	printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
+	printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
 
 	/* Report the memory regions */
 	ram_resource(dev, 3, 0, 640);
@@ -253,7 +253,7 @@ static void mc_read_resources(device_t dev)
 	resource->flags =
 	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
 	    IORESOURCE_ASSIGNED;
-	printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
 		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
 }
 
@@ -289,15 +289,15 @@ static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {
 	case 0xcafebabe:
-		printk_debug("Normal boot.\n");
+		printk(BIOS_DEBUG, "Normal boot.\n");
 		acpi_slp_type=0;
 		break;
 	case 0xcafed00d:
-		printk_debug("S3 Resume.\n");
+		printk(BIOS_DEBUG, "S3 Resume.\n");
 		acpi_slp_type=3;
 		break;
 	default:
-		printk_debug("Unknown boot method, assuming normal.\n");
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
 		acpi_slp_type=0;
 		break;
 	}
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 3f73549eb6..444a360cd3 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -25,7 +25,7 @@
 
 /* Debugging macros. */
 #if CONFIG_DEBUG_RAM_SETUP
-#define PRINTK_DEBUG(x...)	printk_debug(x)
+#define PRINTK_DEBUG(x...)	printk(BIOS_DEBUG, x)
 #else
 #define PRINTK_DEBUG(x...)
 #endif
@@ -74,12 +74,12 @@ static void ram_read32(u32 offset)
 static void sdram_dump_mchbar_registers(void)
 {
 	int i;
-	printk_debug("Dumping MCHBAR Registers\n");
+	printk(BIOS_DEBUG, "Dumping MCHBAR Registers\n");
 
 	for (i=0; i<0xfff; i+=4) {
 		if (MCHBAR32(i) == 0)
 			continue;
-		printk_debug("0x%04x: 0x%08x\n", i, MCHBAR32(i));
+		printk(BIOS_DEBUG, "0x%04x: 0x%08x\n", i, MCHBAR32(i));
 	}
 }
 #endif
@@ -94,7 +94,7 @@ static int memclk(void)
 	case 1: return 400;
 	case 2: return 533;
 	case 3: return 667;
-	default: printk_debug("memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
+	default: printk(BIOS_DEBUG, "memclk: unknown register value %x\n", ((MCHBAR32(CLKCFG) >> 4) & 7) - offset);
 	}
 	return -1;
 }
@@ -106,7 +106,7 @@ static int fsbclk(void)
 	case 0: return 400;
 	case 1: return 533;
 	case 3: return 667;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -118,7 +118,7 @@ static int fsbclk(void)
 	case 0: return 1066;
 	case 1: return 533;
 	case 2: return 800;
-	default: printk_debug("fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
+	default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7);
 	}
 	return -1;
 }
@@ -234,7 +234,7 @@ static void sdram_detect_errors(void)
 
 	if (reg8 & ((1<<7)|(1<<2))) {
 		if (reg8 & (1<<2)) {
-			printk_debug("SLP S4# Assertion Width Violation.\n");
+			printk(BIOS_DEBUG, "SLP S4# Assertion Width Violation.\n");
 			/* Write back clears bit 2 */
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -242,7 +242,7 @@ static void sdram_detect_errors(void)
 		}
 
 		if (reg8 & (1<<7)) {
-			printk_debug("DRAM initialization was interrupted.\n");
+			printk(BIOS_DEBUG, "DRAM initialization was interrupted.\n");
 			reg8 &= ~(1<<7);
 			pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 			do_reset = 1;
@@ -254,7 +254,7 @@ static void sdram_detect_errors(void)
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
 
 		if (do_reset) {
-			printk_debug("Reset required.\n");
+			printk(BIOS_DEBUG, "Reset required.\n");
 			outb(0x00, 0xcf9);
 			outb(0x0e, 0xcf9);
 			for (;;) asm("hlt"); /* Wait for reset! */
@@ -300,10 +300,10 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 
 	if (sdram_capabilities_dual_channel()) {
 		sysinfo->dual_channel = 1;
-		printk_debug("This mainboard supports Dual Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports Dual Channel Operation.\n");
 	} else {
 		sysinfo->dual_channel = 0;
-		printk_debug("This mainboard supports only Single Channel Operation.\n");
+		printk(BIOS_DEBUG, "This mainboard supports only Single Channel Operation.\n");
 	}
 
 	/**
@@ -339,10 +339,10 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 		if (!sdram_capabilities_two_dimms_per_channel() && (i& 1))
 			continue;
 
-		printk_debug("DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
+		printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1));
 
 		if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) {
-			printk_debug("N/A\n");
+			printk(BIOS_DEBUG, "N/A\n");
 			continue;
 		}
 
@@ -360,29 +360,29 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 		case 0x08:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x8DDS\n");
+				printk(BIOS_DEBUG, "x8DDS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS;
 				break;
 			case 0:
-				printk_debug("x8DS\n");
+				printk(BIOS_DEBUG, "x8DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X8DS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		case 0x10:
 			switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) {
 			case 1:
-				printk_debug("x16DS\n");
+				printk(BIOS_DEBUG, "x16DS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16DS;
 				break;
 			case 0:
-				printk_debug("x16SS\n");
+				printk(BIOS_DEBUG, "x16SS\n");
 				sysinfo->dimm[i] = SYSINFO_DIMM_X16SS;
 				break;
 			default:
-				printk_debug ("Unsupported.\n");
+				printk(BIOS_DEBUG, "Unsupported.\n");
 			}
 			break;
 		default:
@@ -397,7 +397,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
 	}
 
 	if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
-		printk_info("Channel 0 has no memory populated.\n");
+		printk(BIOS_INFO, "Channel 0 has no memory populated.\n");
 	}
 }
 
@@ -556,7 +556,7 @@ static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8
 	}
 
 	if (sysinfo->memory_frequency && sysinfo->cas) {
-		printk_debug("Memory will be driven at %dMHz with CAS=%d clocks\n",
+		printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n",
 				sysinfo->memory_frequency, sysinfo->cas);
 	} else {
 		die("Could not find common memory frequency and CAS\n");
@@ -599,7 +599,7 @@ static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRAS error)\n");
 	}
 
-	printk_debug("tRAS = %d cycles\n", tRAS_cycles);
+	printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles);
 	sysinfo->tras = tRAS_cycles;
 }
 
@@ -640,7 +640,7 @@ static void sdram_detect_smallest_tRP(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRP error)\n");
 	}
 
-	printk_debug("tRP = %d cycles\n", tRP_cycles);
+	printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles);
 	sysinfo->trp = tRP_cycles;
 }
 
@@ -680,7 +680,7 @@ static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tRCD error)\n");
 	}
 
-	printk_debug("tRCD = %d cycles\n", tRCD_cycles);
+	printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles);
 	sysinfo->trcd = tRCD_cycles;
 }
 
@@ -720,7 +720,7 @@ static void sdram_detect_smallest_tWR(struct sys_info * sysinfo)
 		die("DDR-II Module does not support this frequency (tWR error)\n");
 	}
 
-	printk_debug("tWR = %d cycles\n", tWR_cycles);
+	printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles);
 	sysinfo->twr = tWR_cycles;
 }
 
@@ -756,7 +756,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 			/* Can this happen? Go back to 127.5ns just to be sure
 			 * we don't run out of the array. This may be wrong
 			 */
-			printk_debug("DIMM %d is 1Gb x16.. Please report.\n", i);
+			printk(BIOS_DEBUG, "DIMM %d is 1Gb x16.. Please report.\n", i);
 			reg8 = 3;
 		}
 
@@ -772,7 +772,7 @@ static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo)
 	}
 
 	sysinfo->trfc = tRFC_cycles[index];
-	printk_debug("tRFC = %d cycles\n", tRFC_cycles[index]);
+	printk(BIOS_DEBUG, "tRFC = %d cycles\n", tRFC_cycles[index]);
 }
 
 static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
@@ -804,7 +804,7 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo)
 
 		die("DDR-II module has unsupported refresh value\n");
 	}
-	printk_debug("Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
+	printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us");
 }
 
 static void sdram_verify_burst_length(struct sys_info * sysinfo)
@@ -1137,18 +1137,18 @@ static void sdram_rcomp_buffer_strength_and_slew(struct sys_info *sysinfo)
 
 	/* Dual Channel needs different tables. */
 	if (sdram_capabilities_dual_channel()) {
-		printk_debug("Programming Dual Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Dual Channel RCOMP\n");
 		strength_multiplier = dual_channel_strength_multiplier;
 		dual_channel = 1;
 		idx = 5 * sysinfo->dimm[0] +  sysinfo->dimm[2];
 	} else {
-		printk_debug("Programming Single Channel RCOMP\n");
+		printk(BIOS_DEBUG, "Programming Single Channel RCOMP\n");
 		strength_multiplier = single_channel_strength_multiplier;
 		dual_channel = 0;
 		idx = 5 * sysinfo->dimm[0] + sysinfo->dimm[1];
 	}
 
-	printk_debug("Table Index: %d\n", idx);
+	printk(BIOS_DEBUG, "Table Index: %d\n", idx);
 
 	MCHBAR8(G1SC) = strength_multiplier[idx * 8 + 0];
 	MCHBAR8(G2SC) = strength_multiplier[idx * 8 + 1];
@@ -1197,7 +1197,7 @@ static void sdram_program_dll_timings(struct sys_info *sysinfo)
 	u32 chan0dll = 0, chan1dll = 0;
 	int i;
 
-	printk_debug ("Programming DLL Timings... \n");
+	printk(BIOS_DEBUG, "Programming DLL Timings... \n");
 
 	MCHBAR16(DQSMT) &= ~( (3 << 12) | (1 << 10) | ( 0xf << 0) );
 	MCHBAR16(DQSMT) |= (1 << 13) | (0xc << 0);
@@ -1249,7 +1249,7 @@ static void sdram_initialize_system_memory_io(struct sys_info *sysinfo)
 	u8 reg8;
 	u32 reg32;
 
-	printk_debug ("Initializing System Memory IO... \n");
+	printk(BIOS_DEBUG, "Initializing System Memory IO... \n");
 	/* Enable Data Half Clock Pushout */
 	reg8 = MCHBAR8(C0HCTC);
 	reg8 &= ~0x1f;
@@ -1291,7 +1291,7 @@ static void sdram_enable_system_memory_io(struct sys_info *sysinfo)
 {
 	u32 reg32;
 
-	printk_debug ("Enabling System Memory IO... \n");
+	printk(BIOS_DEBUG, "Enabling System Memory IO... \n");
 
 	reg32 = MCHBAR32(RCVENMT);
 	reg32 &= ~(0x3f << 6);
@@ -1401,7 +1401,7 @@ static struct dimm_size sdram_get_dimm_size(u16 device)
 	/* Don't die here, I have not come across any of these to test what
 	 * actually happens.
 	 */
-	printk_err("Assymetric DIMMs are not supported by this chipset\n");
+	printk(BIOS_ERR, "Assymetric DIMMs are not supported by this chipset\n");
 
 	sz.side2 -= (rows & 0x0f);		/* Subtract out rows on side 1 */
 	sz.side2 += ((rows >> 4) & 0x0f);	/* Add in rows on side 2 */
@@ -1445,7 +1445,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
 
 		sysinfo->banksize[i * 2] = 1 << (sz.side1 - 28);
 
-		printk_debug("DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
+		printk(BIOS_DEBUG, "DIMM %d side 0 = %d MB\n", i, sysinfo->banksize[i * 2] * 32 );
 
 		if (!sz.side2)
 			continue;
@@ -1456,7 +1456,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo)
 
 		sysinfo->banksize[(i * 2) + 1] = 1 << (sz.side2 - 28);
 
-		printk_debug("DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
+		printk(BIOS_DEBUG, "DIMM %d side 1 = %d MB\n", i, sysinfo->banksize[(i * 2) + 1] * 32);
 	}
 }
 
@@ -1465,7 +1465,7 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 	int i;
 	int cum0, cum1, tolud, tom;
 
-	printk_debug ("Setting RAM size... \n");
+	printk(BIOS_DEBUG, "Setting RAM size... \n");
 
 	cum0 = 0;
 	for(i = 0; i < 2 * DIMM_SOCKETS; i++) {
@@ -1507,9 +1507,9 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo)
 
 	pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);
 
-	printk_debug("C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
-	printk_debug("C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
-	printk_debug("TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
+	printk(BIOS_DEBUG, "C0DRB = 0x%08x\n", MCHBAR32(C0DRB0));
+	printk(BIOS_DEBUG, "C1DRB = 0x%08x\n", MCHBAR32(C1DRB0));
+	printk(BIOS_DEBUG, "TOLUD = 0x%04x\n", pci_read_config8(PCI_DEV(0,0,0), TOLUD));
 
 	pci_write_config16(PCI_DEV(0,0,0), TOM, tom);
 
@@ -1521,7 +1521,7 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
 	int i, value;
 	u16 dra0=0, dra1=0, dra = 0;
 
-	printk_debug ("Setting row attributes... \n");
+	printk(BIOS_DEBUG, "Setting row attributes... \n");
 	for(i=0; i < 2 * DIMM_SOCKETS; i++) {
 		u16 device;
 		u8 columnsrows;
@@ -1561,8 +1561,8 @@ static int sdram_set_row_attributes(struct sys_info *sysinfo)
 	MCHBAR16(C0DRA0) = dra0;
 	MCHBAR16(C1DRA0) = dra1;
 
-	printk_debug("C0DRA = 0x%04x\n", dra0);
-	printk_debug("C1DRA = 0x%04x\n", dra1);
+	printk(BIOS_DEBUG, "C0DRA = 0x%04x\n", dra0);
+	printk(BIOS_DEBUG, "C1DRA = 0x%04x\n", dra1);
 
 	return 0;
 }
@@ -1587,7 +1587,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo)
 		if (sysinfo->banks[i] != 8)
 			continue;
 
-		printk_spew("DIMM%d has 8 banks.\n", i);
+		printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i);
 
 		if (i & 1)
 			MCHBAR16(off32) |= 0x50;
@@ -1852,7 +1852,7 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
 {
 	u32 reg32;
 
-	printk_debug("Setting mode of operation for memory channels...");
+	printk(BIOS_DEBUG, "Setting mode of operation for memory channels...");
 
 	if (sdram_capabilities_interleave() &&
 		    ( ( sysinfo->banksize[0] + sysinfo->banksize[1] +
@@ -1870,21 +1870,21 @@ static void sdram_set_channel_mode(struct sys_info *sysinfo)
 
 	if(sysinfo->interleaved) {
 		/* Dual Channel Interleaved */
-		printk_debug("Dual Channel Interleaved.\n");
+		printk(BIOS_DEBUG, "Dual Channel Interleaved.\n");
 		reg32 |= (1 << 1);
 	} else if (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) {
 		/* Channel 1 only */
-		printk_debug("Single Channel 1 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 1 only.\n");
 		reg32 |= (1 << 2);
 	} else if (sdram_capabilities_dual_channel() && sysinfo->dimm[2] !=
 			SYSINFO_DIMM_NOT_POPULATED) {
 		/* Dual Channel Assymetric */
-		printk_debug("Dual Channel Assymetric.\n");
+		printk(BIOS_DEBUG, "Dual Channel Assymetric.\n");
 		reg32 |= (1 << 0);
 	} else {
 		/* All bits 0 means Single Channel 0 operation */
-		printk_debug("Single Channel 0 only.\n");
+		printk(BIOS_DEBUG, "Single Channel 0 only.\n");
 	}
 
 	reg32 |= (1 << 10);
@@ -1934,14 +1934,14 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 #define VOLTAGE_1_05	0x00
 #define VOLTAGE_1_50	0x01
 
-	printk_debug ("Setting Graphics Frequency... \n");
+	printk(BIOS_DEBUG, "Setting Graphics Frequency... \n");
 
-	printk_debug("FSB: %d MHz ", sysinfo->fsb_frequency);
+	printk(BIOS_DEBUG, "FSB: %d MHz ", sysinfo->fsb_frequency);
 
 	voltage = VOLTAGE_1_05;
 	if (MCHBAR32(DFT_STRAP1) & (1 << 20))
 		voltage = VOLTAGE_1_50;
-	printk_debug("Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
+	printk(BIOS_DEBUG, "Voltage: %s ", (voltage==VOLTAGE_1_05)?"1.05V":"1.5V");
 
 	/* Gate graphics hardware for frequency change */
 	reg8 = pci_read_config16(PCI_DEV(0,2,0), GCFC + 1);
@@ -1971,12 +1971,12 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 			freq = CRCLK_166MHz;
 	}
 
-	printk_debug("Render: ");
+	printk(BIOS_DEBUG, "Render: ");
 	switch (freq) {
-	case CRCLK_166MHz: printk_debug("166Mhz"); break;
-	case CRCLK_200MHz: printk_debug("200Mhz"); break;
-	case CRCLK_250MHz: printk_debug("250Mhz"); break;
-	case CRCLK_400MHz: printk_debug("400Mhz"); break;
+	case CRCLK_166MHz: printk(BIOS_DEBUG, "166Mhz"); break;
+	case CRCLK_200MHz: printk(BIOS_DEBUG, "200Mhz"); break;
+	case CRCLK_250MHz: printk(BIOS_DEBUG, "250Mhz"); break;
+	case CRCLK_400MHz: printk(BIOS_DEBUG, "400Mhz"); break;
 	}
 
 	if (i945_silicon_revision() == 0) {
@@ -2021,10 +2021,10 @@ static void sdram_program_graphics_frequency(struct sys_info *sysinfo)
 
 	if (voltage == VOLTAGE_1_05) {
 		reg8 |= CDCLK_200MHz;
-		printk_debug(" Display: 200MHz\n");
+		printk(BIOS_DEBUG, " Display: 200MHz\n");
 	} else {
 		reg8 |= CDCLK_320MHz;
-		printk_debug(" Display: 320MHz\n");
+		printk(BIOS_DEBUG, " Display: 320MHz\n");
 	}
 	pci_write_config8(PCI_DEV(0,2,0), GCFC, reg8);
 
@@ -2050,21 +2050,21 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
 	offset++;
 #endif
 
-	printk_debug ("Setting Memory Frequency... ");
+	printk(BIOS_DEBUG, "Setting Memory Frequency... ");
 
 	clkcfg = MCHBAR32(CLKCFG);
 
-	printk_debug("CLKCFG=0x%08x, ", clkcfg);
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", clkcfg);
 
 	clkcfg &= ~( (1 << 12) | (1 << 7) | ( 7 << 4) );
 
 	if (sysinfo->mvco4x) {
-		printk_debug("MVCO 4x, ");
+		printk(BIOS_DEBUG, "MVCO 4x, ");
 		clkcfg &= ~(1 << 12);
 	}
 
 	if (sysinfo->clkcfg_bit7) {
-		printk_debug("second VCO, ");
+		printk(BIOS_DEBUG, "second VCO, ");
 
 		clkcfg |= (1 << 7);
 	}
@@ -2077,7 +2077,7 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo)
 	}
 
 	if (MCHBAR32(CLKCFG) == clkcfg) {
-		printk_debug ("ok (unchanged)\n");
+		printk(BIOS_DEBUG, "ok (unchanged)\n");
 		return;
 	}
 
@@ -2118,8 +2118,8 @@ cache_code:
 	goto vco_update;
 out:
 
-	printk_debug("CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
-	printk_debug ("ok\n");
+	printk(BIOS_DEBUG, "CLKCFG=0x%08x, ", MCHBAR32(CLKCFG));
+	printk(BIOS_DEBUG, "ok\n");
 }
 
 static void sdram_program_clock_crossing(void)
@@ -2222,28 +2222,28 @@ static void sdram_program_clock_crossing(void)
 	};
 #endif
 
-	printk_debug("Programming Clock Crossing...");
+	printk(BIOS_DEBUG, "Programming Clock Crossing...");
 
-	printk_debug("MEM=");
+	printk(BIOS_DEBUG, "MEM=");
 	switch (memclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 2; break;
-	case 667:	printk_debug("667"); idx += 4; break;
-	default: printk_debug("RSVD %x", memclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 2; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 4; break;
+	default: printk(BIOS_DEBUG, "RSVD %x", memclk()); return;
 	}
 
-	printk_debug(" FSB=");
+	printk(BIOS_DEBUG, " FSB=");
 	switch (fsbclk()) {
-	case 400:	printk_debug("400"); idx += 0; break;
-	case 533:	printk_debug("533"); idx += 6; break;
-	case 667:	printk_debug("667"); idx += 12; break;
-	case 800:	printk_debug("800"); idx += 18; break;
-	case 1066:	printk_debug("1066"); idx += 24; break;
-	default: printk_debug("RSVD %x\n", fsbclk()); return;
+	case 400:	printk(BIOS_DEBUG, "400"); idx += 0; break;
+	case 533:	printk(BIOS_DEBUG, "533"); idx += 6; break;
+	case 667:	printk(BIOS_DEBUG, "667"); idx += 12; break;
+	case 800:	printk(BIOS_DEBUG, "800"); idx += 18; break;
+	case 1066:	printk(BIOS_DEBUG, "1066"); idx += 24; break;
+	default: printk(BIOS_DEBUG, "RSVD %x\n", fsbclk()); return;
 	}
 
 	if (command_clock_crossing[idx]==0xffffffff) {
-		printk_debug("Invalid MEM/FSB combination!\n");
+		printk(BIOS_DEBUG, "Invalid MEM/FSB combination!\n");
 	}
 
 	MCHBAR32(CCCFT + 0) = command_clock_crossing[idx];
@@ -2254,7 +2254,7 @@ static void sdram_program_clock_crossing(void)
 	MCHBAR32(C1DCCFT + 0) = data_clock_crossing[idx];
 	MCHBAR32(C1DCCFT + 4) = data_clock_crossing[idx + 1];
 
-	printk_debug("... ok\n");
+	printk(BIOS_DEBUG, "... ok\n");
 }
 
 static void sdram_disable_fast_dispatch(void)
@@ -2569,7 +2569,7 @@ static void sdram_power_management(struct sys_info *sysinfo)
 #ifdef C2_SELF_REFRESH_DISABLE
 
 	if (integrated_graphics) {
-		printk_debug("C2 self-refresh with IGD\n");
+		printk(BIOS_DEBUG, "C2 self-refresh with IGD\n");
 		MCHBAR16(MIPMC4) = 0x0468;
 		MCHBAR16(MIPMC5) = 0x046c;
 		MCHBAR16(MIPMC6) = 0x046c;
@@ -2728,7 +2728,7 @@ static void sdram_on_die_termination(struct sys_info *sysinfo)
 
 	if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED &&
 			sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {
-		printk_debug("one dimm per channel config.. \n");
+		printk(BIOS_DEBUG, "one dimm per channel config.. \n");
 
 		reg32 = MCHBAR32(C0ODT);
 		reg32 &= ~(7 << 28);
@@ -2832,7 +2832,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
 			continue;
 		}
 
-		printk_debug("jedec enable sequence: bank %d\n", i);
+		printk(BIOS_DEBUG, "jedec enable sequence: bank %d\n", i);
 		switch (i) {
 		case 0:
 			/* Start at address 0 */
@@ -2845,7 +2845,7 @@ static void sdram_jedec_enable(struct sys_info *sysinfo)
 			}
 		default:
 			if (nonzero != -1) {
-				printk_debug("bankaddr from bank size of rank %d\n", nonzero);
+				printk(BIOS_DEBUG, "bankaddr from bank size of rank %d\n", nonzero);
 				bankaddr += sysinfo->banksize[nonzero] <<
 					(sysinfo->interleaved ? 26 : 25);
 				break;
@@ -3010,7 +3010,7 @@ void sdram_initialize(int boot_path)
 
 	sdram_detect_errors();
 
-	printk_debug ("Setting up RAM controller.\n");
+	printk(BIOS_DEBUG, "Setting up RAM controller.\n");
 
 	memset(&sysinfo, 0, sizeof(sysinfo));
 
@@ -3131,7 +3131,7 @@ void sdram_initialize(int boot_path)
 	reg8 &= ~(1 << 7);
 	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8);
 
-	printk_debug("RAM initialization finished.\n");
+	printk(BIOS_DEBUG, "RAM initialization finished.\n");
 
 	sdram_setup_processor_side();
 }
diff --git a/src/northbridge/intel/i945/rcven.c b/src/northbridge/intel/i945/rcven.c
index 846af4f080..a912b2695f 100644
--- a/src/northbridge/intel/i945/rcven.c
+++ b/src/northbridge/intel/i945/rcven.c
@@ -67,7 +67,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
 {
 	u32 reg32;
 
-	printk_spew("    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
+	printk(BIOS_SPEW, "    set_receive_enable() medium=0x%x, coarse=0x%x\n", medium, coarse);
 
 	reg32 = MCHBAR32(C0DRT1 + channel_offset);
 	reg32 &= 0xf0ffffff;
@@ -76,7 +76,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
 
 	/* This should never happen: */
 	if (coarse > 0x0f)
-		printk_debug("set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
+		printk(BIOS_DEBUG, "set_receive_enable: coarse overflow: 0x%02x.\n", coarse);
 
 	/* medium control
 	 *
@@ -102,7 +102,7 @@ static void set_receive_enable(int channel_offset, u8 medium, u8 coarse)
 
 static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  normalize()\n");
+	printk(BIOS_SPEW, "  normalize()\n");
 
 	if (*fine < 0x80)
 		return 0;
@@ -111,7 +111,7 @@ static int normalize(int channel_offset, u8 * mediumcoarse, u8 * fine)
 	*mediumcoarse += 1;
 
 	if (*mediumcoarse >= 0x40) {
-		printk_debug("Normalize Error\n");
+		printk(BIOS_DEBUG, "Normalize Error\n");
 		return -1;
 	}
 
@@ -129,11 +129,11 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
 	/* find start of the data phase */
 	u32 reg32;
 
-	printk_spew("  find_preamble()\n");
+	printk(BIOS_SPEW, "  find_preamble()\n");
 
 	do {
 		if (*mediumcoarse < 4) {
-			printk_debug("No Preamble found.\n");
+			printk(BIOS_DEBUG, "No Preamble found.\n");
 			return -1;
 		}
 		*mediumcoarse -= 4;
@@ -146,7 +146,7 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
 	} while (reg32 & (1 << 19));
 
 	if (!(reg32 & (1 << 18))) {
-		printk_debug("No Preamble found (neither high nor low).\n");
+		printk(BIOS_DEBUG, "No Preamble found (neither high nor low).\n");
 		return -1;
 	}
 
@@ -159,14 +159,14 @@ static int find_preamble(int channel_offset, u8 * mediumcoarse,
 
 static int add_quarter_clock(int channel_offset, u8 * mediumcoarse, u8 * fine)
 {
-	printk_spew("  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
+	printk(BIOS_SPEW, "  add_quarter_clock() mediumcoarse=%02x fine=%02x\n",
 			*mediumcoarse, *fine);
 	if (*fine >= 0x80) {
 		*fine -= 0x80;
 
 		*mediumcoarse += 2;
 		if (*mediumcoarse >= 0x40) {
-			printk_debug("clocks at max.\n");
+			printk(BIOS_DEBUG, "clocks at max.\n");
 			return -1;
 		}
 
@@ -186,7 +186,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
 {
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_low()\n");
+	printk(BIOS_SPEW, "  find_strobes_low()\n");
 
 	for (;;) {
 		MCHBAR8(C0WL0REOST + channel_offset) = *fine;
@@ -211,7 +211,7 @@ static int find_strobes_low(int channel_offset, u8 * mediumcoarse, u8 * fine,
 
 	}
 
-	printk_debug("Could not find low strobe\n");
+	printk(BIOS_DEBUG, "Could not find low strobe\n");
 	return 0;
 }
 
@@ -222,7 +222,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
 	int counter;
 	u32 rcvenmt;
 
-	printk_spew("  find_strobes_edge()\n");
+	printk(BIOS_SPEW, "  find_strobes_edge()\n");
 
 	counter = 8;
 	set_receive_enable(channel_offset, *mediumcoarse & 3,
@@ -257,7 +257,7 @@ static int find_strobes_edge(int channel_offset, u8 * mediumcoarse, u8 * fine,
 			continue;
 		}
 
-		printk_debug("Could not find rising edge.\n");
+		printk(BIOS_DEBUG, "Could not find rising edge.\n");
 		return -1;
 	}
 
@@ -286,7 +286,7 @@ static int receive_enable_autoconfig(int channel_offset,
 	u8 mediumcoarse;
 	u8 fine;
 
-	printk_spew("receive_enable_autoconfig() for channel %d\n",
+	printk(BIOS_SPEW, "receive_enable_autoconfig() for channel %d\n",
 		    channel_offset ? 1 : 0);
 
 	/* Set initial values */
@@ -315,7 +315,7 @@ static int receive_enable_autoconfig(int channel_offset,
 	 * It can be removed when the output message is not printed anymore
 	 */
 	if (MCHBAR8(C0WL0REOST + channel_offset) == 0) {
-		printk_debug("Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
+		printk(BIOS_DEBUG, "Weird. No C%sWL0REOST\n", channel_offset?"1":"0");
 	}
 
 	return 0;