diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-11-07 11:39:58 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-12-05 14:22:12 +0000 |
| commit | 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 (patch) | |
| tree | 4d23f557990d8edb3edb1b09e2be3cd609b6acd7 /src/northbridge/intel/i945 | |
| parent | 6f573217a0920b18ea9febd9c6696a01b0f7c082 (diff) | |
cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm
C5, C6 and slfm depend on the southbridge and the northbridge to be able
to provide this functionality, with some just lacking the possibility to
do so. Move the devicetree configuration to the southbridge.
This removes the need for a magic lapic in the devicetree.
Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index c175576d3a..00276562d8 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -10,6 +10,7 @@ #include <device/pci_ids.h> #include <acpi/acpi.h> #include <cpu/intel/smm_reloc.h> +#include <cpu/intel/speedstep.h> #include "i945.h" static void mch_domain_read_resources(struct device *dev) @@ -164,3 +165,8 @@ struct device_operations i945_cpu_bus_ops = { struct chip_operations northbridge_intel_i945_ops = { CHIP_NAME("Intel i945 Northbridge") }; + +bool northbridge_support_slfm(void) +{ + return false; +} |