diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-02-06 15:08:04 +0100 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2017-02-14 13:03:02 +0100 |
| commit | d81078d944bd78b1dca559444d938f18d4004205 (patch) | |
| tree | 4ae3c9b7f6b727114b21b1ad6b60769534e883e3 /src/northbridge/intel/i945 | |
| parent | e2143cdf5a95032809449722950e503740973a56 (diff) | |
nb/i945/gma.c: Remove writes to FIFO Watermark registers
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18294
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/gma.c | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 0d4ca43443..eac8717cde 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -293,14 +293,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + DSPPOS(0), 0); /* Backlight init. */ - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(mmiobase + FW_BLC, 0x011d011a); - write32(mmiobase + FW_BLC2, 0x00000102); - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); - write32(mmiobase + FW_BLC_SELF, 0x0001003f); - write32(mmiobase + FW_BLC, 0x011d0109); - write32(mmiobase + FW_BLC2, 0x00000102); - write32(mmiobase + FW_BLC_SELF, FW_BLC_SELF_EN_MASK); write32(mmiobase + BLC_PWM_CTL, conf->gpu_backlight); edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; |