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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-06-27 13:24:11 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-11-11 18:43:10 +0100 |
| commit | a4ffe9dda0eb50eb698fef303f426408338fa0ff (patch) | |
| tree | e8e7026a1cc0c3e5e3929e47905015da524e3011 /src/northbridge/intel/i945 | |
| parent | 9b9915284f5070c6f664fa36495ae831e95ea819 (diff) | |
intel post-car: Separate files for setup_stack_and_mtrrs()
Have a common romstage.c file to prepare CAR stack guards.
MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.
Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/ram_calc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 4349d19ea7..39ede5f75b 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -20,6 +20,7 @@ #include <cbmem.h> #include "i945.h" #include <console/console.h> +#include <cpu/intel/romstage.h> static uintptr_t smm_region_start(void) { @@ -69,3 +70,8 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } + +void *setup_stack_and_mtrrs(void) +{ + return (void*)CONFIG_RAMTOP; +} |