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| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-16 10:01:33 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-24 14:10:00 +0000 |
| commit | 2119d0ba4345a19b9db7dc13e36f3fa57f75d234 (patch) | |
| tree | aeeef324906730e350c338edb4f5704f20a95385 /src/northbridge/intel/i945 | |
| parent | ebdf298ec2dd84810a37a4aac154200b2102b394 (diff) | |
treewide: Capitalize 'CMOS'
Change-Id: I1d36e554618498d70f33f6c425b0abc91d4fb952
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38928
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 1deca3eeba..44d25846c2 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -161,7 +161,7 @@ static void i945_setup_bars(void) pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1); - /* vram size from cmos option */ + /* vram size from CMOS option */ if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) gfxsize = 2; /* 2 for 8MB */ /* make sure no invalid setting is used */ |