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authorArthur Heymans <arthur@aheymans.xyz>2017-03-09 11:30:23 +0100
committerMartin Roth <martinroth@google.com>2017-03-22 17:55:37 +0100
commit70a8e34853d4b01ab7a2089821c35715c59b4415 (patch)
treeb39e19d126491bdf23a2026cc58374b019d169cb /src/northbridge/intel/i945/ram_calc.c
parent219daafa8fc27483b2a652d9428d874bf960a6a1 (diff)
nb/intel/i945: Fix errors found by checkpatch.pl
Change-Id: Ic2dd40e73d4a4c091c5ce1f49bbf9ab4d013d7af Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18704 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/northbridge/intel/i945/ram_calc.c')
-rw-r--r--src/northbridge/intel/i945/ram_calc.c11
1 files changed, 5 insertions, 6 deletions
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c
index a8ef065fb2..0c337bb54e 100644
--- a/src/northbridge/intel/i945/ram_calc.c
+++ b/src/northbridge/intel/i945/ram_calc.c
@@ -29,15 +29,14 @@ static uintptr_t smm_region_start(void)
{
uintptr_t tom;
- if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) {
+ if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1))
/* IGD enabled, get top of Memory from BSM register */
- tom = pci_read_config32(PCI_DEV(0,2,0), BSM);
- } else {
- tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24;
- }
+ tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM);
+ else
+ tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24;
/* if TSEG enabled subtract size */
- switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
+ switch (pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM) & 0x07) {
case 0x01:
/* 1MB TSEG */
tom -= 0x100000;